Anti-fuse Memory Cell Programming Accuracy via Localized Breakdown
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Solution Overview
Problem
Anti-fuse one-time programmable memory cells face challenges in accurately reading programmed data due to random rupture positions of the gate oxide layer, leading to misjudgments and high leakage currents, especially when only a permanent conductive path with higher resistance is formed.
Innovation Solution
The design includes a substrate with a well region, a selection transistor, and a programmable transistor, where the N-type lightly doped drains are strategically positioned to increase the likelihood of forming a permanent conductive path with lower resistance, and additional features like insulated transistors and isolation regions to reduce leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the gate oxide layer rupture position is random during programming operation, then the programming operation can be performed, but the conduction current becomes unpredictable leading to misjudgment by sense amplifier
Solution Approach 1:
The patent introduces a preliminary breakdown region formed in the lightly doped drain before programming operation. This pre-formed region serves as a predetermined breakdown location that guides where the gate oxide layer will rupture during programming. By preparing this region in advance, the patent ensures that breakdown occurs at a specific location rather than randomly, thereby guaranteeing formation of the desired permanent conductive path with appropriate resistance characteristics for reliable sense amplifier detection.
2Ease of manufacture
If only permanent conductive path with higher resistance is formed, then the programming operation is completed, but the conduction current is too small for sense amplifier to detect accurately
Solution Approach 1:
The patent modifies the local properties of the lightly doped drain by introducing a preliminary breakdown region with specific doping characteristics in that localized area. This creates a region with different electrical properties (lower resistance) compared to the rest of the structure. When breakdown occurs in this specially prepared region, it forms a permanent conductive path with lower resistance that allows sufficient conduction current to flow for reliable sense amplifier detection, while the rest of the device maintains its normal structure.
3Ease of manufacture
If the gate oxide layer breaks down between gate structure and P well region, then permanent conductive path is formed, but leakage current increases between memory cells
Solution Approach 1:
The patent applies local quality modification by concentrating the breakdown phenomenon in a specifically engineered region (the preliminary breakdown region in the lightly doped drain) rather than allowing it to occur anywhere in the device. This localized approach ensures that permanent conductive paths are formed only in intended locations with proper isolation, preventing leakage current between adjacent memory cells while still achieving the desired programming effect.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the accuracy of read operations by increasing the probability of forming a conductive path with lower resistance, allowing for larger conduction currents to be sensed, and reduces leakage currents between memory cells, improving overall memory cell performance.
Implementation Method 1
The induced voltage results in breakdown occurring in the gate oxide layer (or gate dielectric layer) of the gate structure 103 of the programmable transistor 12 causing the gate oxide layer to rupture
Data Source
AI summary
An anti-fuse memory cell is provided. The anti-fuse memory cell includes a programmable transistor and a selection transistor. The programmable transistor includes a gate structure, a first doped region and a lightly doped region. The first doped region is divided into a first portion doped region, a second portion doped region and a third portion doped region. The first and second portion doped regions are respectively a source and a drain of the programmable transistor, and the third portion doped region is disposed between the first and second portion doped regions. The lightly doped region is distributed around a channel region of the programmable transistor, and adjacent to the first, second and third portion doped regions. The selection transistor includes a gate structure and a second doped region, and connected in series to the programmable transistor through the first portion doped region.