Antifuse Memory Programming Circuit Reduces Write Time
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Solution Overview
Problem
Conventional non-volatile semiconductor memory devices, such as those using gate-insulating film breakdown antifuse OTP memories, face challenges in reducing programming time due to limitations in programming voltage and current supply, especially when dealing with megabit-order data capacities, which increases development and manufacturing costs and delays product introduction.
Innovation Solution
A non-volatile semiconductor memory device with a control circuit that applies a programming voltage to selected word-lines while grounding bit-lines connected to memory cells, allowing concurrent programming of multiple cells, and subsequently adjusts voltages based on cell states to optimize programming time and reduce unnecessary stress on unprogrammed cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate-insulating film breakdown antifuse OTP memories are used, then non-volatile storage is achieved, but programming time becomes excessively long for megabit-order data capacities
Solution Approach 1:
The patent segments the memory array into multiple blocks that can be programmed concurrently. By dividing the memory structure and enabling parallel programming operations across different blocks, the total programming time is reduced while maintaining reliable non-volatile storage through the antifuse mechanism in each cell.
Solution Approach 2:
The patent combines multiple programming operations into a single concurrent process. By merging the programming of multiple memory cells into one operation using shared word lines and bit lines, the system achieves faster programming throughput without compromising the reliability of individual cell storage.
2Loss of time
If higher programming voltage is applied to speed up programming, then programming time is reduced, but programming current increases excessively causing harmful effects
Solution Approach 1:
The patent applies different voltage levels to different parts of the memory array during programming. By controlling which word lines and bit lines receive high voltage versus low voltage, the system achieves fast programming in selected cells while preventing excessive current from flowing through unprogrammed cells, thus reducing harmful effects.
Solution Approach 2:
Instead of applying high voltage to all memory cells simultaneously (which would cause excessive current), the patent inverts the approach by applying high voltage only to specific word lines while keeping other bit lines at low voltage. This selective inversion of voltage application enables fast programming without the harmful current effects.
3Loss of time
If conventional sequential programming is used, then programming current is controlled, but programming time becomes excessively long
Solution Approach 1:
The patent introduces dynamic voltage control during the programming process. By changing voltage levels from static sequential programming to dynamic concurrent programming, the system can program multiple cells simultaneously while maintaining control over current flow. The control circuit dynamically adjusts which lines receive high voltage based on the programming state, achieving both speed and control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables faster programming of multiple memory cells concurrently, reducing overall programming time and minimizing the increase in programming current, thus lowering development and manufacturing costs and improving product timeliness.
Implementation Method 1
This type of memory applies a high voltage to a gate-insulating film of a MOSFET to cause a dielectric breakdown, thus forming a conductive spot that reduces the resistance of the element
Implementation Method 2
The programming operation includes a first operation of applying the programming voltage... and a second operation of generating a Joule heat effect
Data Source
AI summary
A device includes a memory cell array and a control circuit, the memory cell array including word-lines, bit-lines, and memory cells arranged at the intersections of the word-lines and the bit-lines, each memory cell including an electrically programmable antifuse element. The control circuit may perform, as a first step, applying a programming voltage to one of the word-lines while applying a ground voltage to bit-lines each connected to respective selected memory cells, and as a second step, after the first step, keeping one of the one word-lines at the programming voltage while concurrently reading the electrical states of the selected memory cells, and according to the read electrical states, applying the ground voltage again to a bit-line connected to an unprogrammed selected memory cell after the first step, and applying a voltage higher than the ground voltage to a bit-line connected to a programmed selected memory cell after the first step.