Anti-Fuse Memory Cell Segmentation for Yield and Area
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Solution Overview
Problem
Current semiconductor memory devices face challenges in yield and area efficiency when using electric fuses (anti-fuses) for storing fail addresses, particularly due to issues with the twin cell scheme's connection yield and increased connection time interval, which result in defective bits and inefficient data retrieval.
Innovation Solution
A semiconductor device configuration that includes first and second anti-fuses connected between different nodes, with specific voltage applications during programming operations to improve yield and reduce area, allowing for independent connection and loading of each anti-fuse, thereby enhancing the reliability and efficiency of data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the twin cell scheme is used to store one bit by two AF cells connected in parallel, then the area is reduced by about forty-nine percent compared to the OR cell scheme, but the connection yield deteriorates and dropout or failure bits occur
Solution Approach 1:
The patent divides the anti-fuse storage system into separate independent cells (first AF cell and second AF cell) with distinct connection paths. Each cell has its own bit line connection, allowing independent programming and reading operations. This segmentation eliminates the mutual interference and dropout issues that occur in parallel-connected twin cell schemes, while maintaining compact area through shared word line and column selection circuitry.
Solution Approach 2:
The patent introduces a column selection circuit as an intermediary component that selectively connects either the first bit line or the second bit line to the read amplifier based on the state of the anti-fuse cells. This intermediary mechanism enables reliable detection of stored data without requiring direct parallel connection between the two AF cells, thereby solving the dropout problem while maintaining area efficiency.
2Area of stationary object
If the OR withdrawn scheme is used to store one bit by one AF cell, then the area is reduced by about fifty-three percent compared to the OR cell scheme, but the connection yield deteriorates and it is necessary to prolong the connection time interval up to 20 milliseconds or more
Solution Approach 1:
The patent uses two separate anti-fuse cells instead of a single AF cell, with each cell having its own dedicated bit line connection. This segmentation allows parallel programming operations and eliminates the need for prolonged connection time intervals required by the OR withdrawn scheme, while achieving comparable area reduction through efficient sharing of common circuitry.
Solution Approach 2:
The patent changes the operational parameters by applying high voltage to the word line and selecting specific bit lines through the column selection circuit, enabling rapid programming and reading operations. This parameter-based control mechanism eliminates the need for extended connection time intervals (20 milliseconds or more) that are necessary in the OR withdrawn scheme, achieving faster operation with reduced area.
3Reliability
If electric fuses (anti-fuses) are used for storing fail addresses, then the reliability of moisture resistance is improved and process management is simplified, but the area efficiency deteriorates due to the twin cell scheme's connection issues
Solution Approach 1:
The patent segments the anti-fuse storage into independent first and second AF cells with separate bit line connections, eliminating the connection yield problems that reduce area efficiency in conventional twin cell schemes. This segmentation maintains the reliability advantages of anti-fuses (moisture resistance, simplified process management) while achieving better area efficiency through independent cell operation and shared common circuitry.
Solution Approach 2:
The patent implements multi-functionality by having both the first and second AF cells share common word line, column selection circuit, and read amplifier resources. This universal sharing of circuitry enables the system to maintain high reliability through anti-fuse technology while improving area efficiency, as the same hardware resources serve multiple storage functions rather than requiring dedicated circuits for each cell.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution achieves improved yield and reduced area requirements, comparable to the OR cell scheme, while maintaining the reliability of the twin cell scheme, by allowing for effective connection and loading of anti-fuses, thus addressing the limitations of existing schemes.
Implementation Method 1
The anti-fuse comprises a fuse in which a high voltage is applied to an insulator such as an oxide film to break down the insulator to cause conduction
Data Source
AI summary
A device includes a first power supply line supplying a first voltage, first, second, and third nodes, a selection circuit connected between the first power supply line and the first node, a first anti-fuse connected between the first node and the second node, and a second anti-fuse connected between the first node and the third node. The second node and the third node are not connected to each other.