Antifuse Memory Cell Array Area Reduction via Shared Select Transistors
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Solution Overview
Problem
As the integration density of memory systems increases, the area required for antifuse memory devices also grows, affecting layout and reliability, necessitating a method to reduce the area while maintaining reliability.
Innovation Solution
The antifuse memory device shares a switch for accessing antifuse memory cells, utilizing parallel antifuse transistors and a select transistor to perform programming operations in multiple sub-steps, reducing circuit area and improving reliability by compensating for errors and defects during programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the integration density of memory systems is increased, then the number of memory cells increases, but the circuit area for intellectual property increases
Solution Approach 1:
The patent merges multiple select transistors into a shared select transistor that is commonly used by multiple antifuse memory cells. This consolidation reduces the total number of transistors required in the memory array, thereby decreasing the circuit area while maintaining the capability to access and program individual memory cells through selective activation.
Solution Approach 2:
The shared select transistor serves multiple functions by being accessible to multiple antifuse memory cells. A single select transistor can select and control different memory cells at different times through the application of appropriate voltages to different word lines, eliminating the need for dedicated select transistors for each memory cell.
2Quantity of substance
If the number of memory cells increases, then integration density improves, but reliability of program operation may deteriorate
Solution Approach 1:
The patent divides the programming operation into multiple sequential sub-steps: a first programming sub-step that applies a first voltage to program the selected antifuse memory cell, and a second programming sub-step that applies a second voltage to verify or complete the programming. This segmentation allows for error detection and correction, improving the reliability of program operations.
Solution Approach 2:
The multi-step programming process incorporates feedback mechanisms where the result of the first programming sub-step can be evaluated before proceeding to the second sub-step. This feedback approach ensures that programming errors are detected and corrected, thereby improving overall program operation reliability.
3Area of stationary object
If select transistors are shared among multiple antifuse memory cells, then circuit area is reduced, but access control complexity increases
Solution Approach 1:
The patent employs dynamic voltage control to manage access to shared select transistors. By dynamically applying different voltages to different word lines at different times, the system can selectively activate specific memory cells connected to shared select transistors. This dynamic control approach simplifies the access control logic compared to static dedicated connections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the area of the antifuse memory device, enhances programming reliability, and simplifies the logic circuit structure by sharing select transistors, thereby improving overall device efficiency and data storage capabilities.
Implementation Method 1
an antifuse may be coupled through a process of breaking a dielectric material by applying a high voltage to a metal oxide semiconductor (MOS) capacitor
Data Source
AI summary
A memory device includes a memory cell array comprising a plurality of antifuse memory cells coupled to a plurality of word lines, a plurality of voltage lines and a plurality of bit lines, and a first decoder suitable for generating a word line driving signal associated with a target memory cell among the plurality of antifuse memory cells in response to a first address, and asserting the word line driving signal at least twice during a program operation.