Anti-Fuse Memory State Detection Circuit
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Solution Overview
Problem
The existing state detection methods for anti-fuse memory cells are prone to inaccuracies due to fluctuations in resistance caused by process, voltage, and temperature variations, leading to misjudgments of burned or non-burned cells, which affects yield.
Innovation Solution
A state detection circuit comprising an amplifier, anti-fuse memory cell array, switch elements, and a comparator, where the resistance of the anti-fuse memory cell is converted to a linear current source, and the voltage of a node is compared with a reference voltage at a controlled time point to accurately determine the storage state, thereby stabilizing the detection process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a simple logic gate circuit is used for state detection, then the device complexity is reduced, but the measurement precision deteriorates due to detection errors caused by resistance and voltage fluctuations
Solution Approach 1:
An amplifier is introduced as an intermediary component between the anti-fuse memory cell and the logic gate circuit. The amplifier converts the resistance variation of the anti-fuse memory cell into a voltage signal that is amplified to a level suitable for logic gate input, thereby improving detection precision without significantly increasing overall circuit complexity
Solution Approach 2:
The detection method changes the parameter being measured from direct resistance measurement to voltage measurement at a specific node. By transforming the resistance parameter into a voltage parameter through the amplifier and controlling the measurement timing, the system achieves more stable and accurate detection results
2Speed
If detection is performed at any time point, then the detection speed is improved, but the measurement precision deteriorates due to voltage fluctuations at different times
Solution Approach 1:
The system performs preliminary actions by first applying a programming pulse to the anti-fuse memory cell, then waiting for a specific duration before taking the detection measurement. This timing control ensures that the detection occurs at an optimal moment when the voltage level is stable and reflects the true storage state, thereby improving measurement precision
Solution Approach 2:
The detection circuit includes a feedback mechanism where the voltage at the first node is continuously monitored and compared against reference voltages. The feedback signal from the amplifier and comparator circuits allows the system to adjust detection timing and ensure accurate measurement, improving both precision and reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the accuracy of state detection for anti-fuse memory cells by stabilizing the detection process, reducing errors caused by resistance and voltage fluctuations, and improving yield by precisely determining the storage state.
Implementation Method 1
a path current flows through equivalent resistance under the storage state, and a relatively low voltage is generated at a node 1
Implementation Method 2
a voltage drop generated by a fixed circuit on the path will exceed a flipping point of the logic gate 12
Data Source
AI summary
A state detection circuit for an anti-fuse memory cell includes: amplifier, having first input terminal connected with first reference voltage, second input terminal connected with first node and output terminal connected with second node; anti-fuse memory cell array, including anti-fuse memory cell sub-arrays, bit lines of sub-arrays are connected with first node, word lines of sub-arrays are connected with controller and each sub-array includes anti-fuse memory cells; first switch element, having first terminal connected with power supply, second terminal connected with first node and control terminal connected with second node; second switch element, having first terminal connected with power supply, second terminal connected with third node and control terminal connected with second node; third switch element, having first terminal connected with third node, grounded second terminal and control terminal connected with controller; and comparator, having first and second input terminals connected with third node and second reference voltage respectively.