Anti-Fuse Memory Cell Nanostructure Width Split for Read Accuracy
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Solution Overview
Problem
In contemporary semiconductor device fabrication, non-planar transistor architectures like nanostructure transistors offer improved performance and density, but existing anti-fuse memory cells face challenges in programming yield and reading accuracy due to the size of the gate dielectric area and the ratio of Ion to Ioff currents.
Innovation Solution
The proposed memory device incorporates a programming transistor with narrower nanostructure channels and reading transistors with wider nanostructure channels, enhancing the programming yield and reading accuracy by optimizing the gate dielectric area and current conduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate dielectric area is reduced to improve programming yield, then programming yield is improved, but reading accuracy deteriorates due to insufficient current differentiation
Solution Approach 1:
The patent applies different nanostructure widths to different transistor types within the same memory cell. Programming transistors use narrower nanostructures (e.g., 5-10 nm) to reduce gate dielectric area and improve programming yield, while reading transistors use wider nanostructures (e.g., 15-20 nm) to increase current conduction capability and improve reading accuracy. This local differentiation resolves the contradiction by optimizing each transistor's geometry for its specific function.
Solution Approach 2:
The patent changes the physical parameter of nanostructure width to simultaneously address both programming and reading requirements. By varying the width parameter across different transistor instances, the gate dielectric area is reduced for programming transistors (improving programming yield) while reading transistors maintain sufficient area for accurate current measurement (improving reading accuracy).
2Measurement precision
If the gate dielectric area is increased to improve reading accuracy, then reading accuracy is improved, but programming yield deteriorates due to higher breakdown probability
Solution Approach 1:
The patent implements local quality differentiation by assigning narrower nanostructure widths specifically to programming transistors, reducing their gate dielectric area and consequently lowering the probability of dielectric breakdown during programming. This localized optimization improves programming yield without compromising the gate dielectric area of reading transistors, which maintain wider dimensions for accurate current measurement.
3Ease of manufacture
If uniform nanostructure width is used for all transistors, then manufacturing simplicity is maintained, but performance is compromised due to insufficient current differentiation between programming and reading operations
Solution Approach 1:
The patent overcomes the limitation of uniform manufacturing by implementing local quality variations through selective nanostructure width assignment. Different width values are assigned to programming versus reading transistors based on their functional requirements, enabling optimized performance for both operations while maintaining compatibility with standard fabrication processes through parameter specification in the device layout.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the programming yield and enlarges the reading window, allowing for better differentiation between logic states, thus enhancing the overall performance of anti-fuse memory cells.
Implementation Method 1
A gate dielectric of the programming MOS transistor may be broken down to cause the gate and the source or drain sub-feature of the programming MOS transistor to be interconnected
Data Source
AI summary
A memory device includes a first transistor. The first transistor includes one or more first semiconductor nanostructures spaced apart from one another along a first direction. Each of the one or more first semiconductor nanostructures has a first width along a second direction perpendicular to the first direction. The memory device also includes a second transistor coupled to the first transistor in series. The second transistor includes one or more second semiconductor nanostructures spaced apart from one another along the first direction. Each of the one or more second semiconductor nanostructures has a second, different width along the second direction.