Anti-Fuse and MIM Capacitor Integration in Semiconductor RDL
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Solution Overview
Problem
The complexity and cost of manufacturing semiconductor devices with integrated programmable links, such as fuse and anti-fuse structures, pose challenges in enhancing performance and integration while reducing overall size and manufacturing costs.
Innovation Solution
A semiconductor device incorporating an anti-fuse structure and metal-insulator-metal (MIM) capacitors connected to a redistribution layer (RDL), where the MIM capacitors are integrally formed with the RDL, and a passivation layer with an air gap between conductive portions, allowing for reduced size and increased integration by forming conductive filaments upon programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fuse or anti-fuse structures are integrated into semiconductor devices for programmable links, then fault tolerance and programmability are improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines the anti-fuse structure with MIM capacitor structures and redistribution layers into a unified integrated design. The first conductive portion, second conductive portion, and passivation layer form the anti-fuse, while MIM capacitors are formed using metal layers and insulating layers that are also part of the interconnect structure. This merging of functions reduces the number of separate manufacturing processes and simplifies the overall device architecture.
Solution Approach 2:
The metal layers in the device serve multiple functions: they form the electrodes of MIM capacitors, create redistribution layers for electrical connections, and establish interconnect pathways. The insulating layers serve as both dielectric materials for capacitors and as isolation layers for the anti-fuse structure. This multi-functionality reduces the need for dedicated structures and simplifies manufacturing.
2Adaptability or versatility
If more programmable links and functional elements are integrated, then device functionality and versatility are improved, but overall device size increases
Solution Approach 1:
The patent implements a nested structure where MIM capacitors are formed within the same vertical space as the anti-fuse structure. The metal layers of the MIM capacitors are embedded between insulating layers that are already present in the device stack, allowing capacitive elements to be nested within the interconnect architecture without requiring additional lateral space.
Solution Approach 2:
The patent transitions from planar integration to three-dimensional integration by stacking multiple metal layers and insulating layers vertically. The MIM capacitors are formed in the vertical dimension using stacked metal-insulator-metal layers, while the anti-fuse structure utilizes the vertical passivation layer. This vertical stacking allows multiple functional elements to occupy the same lateral footprint, significantly reducing device area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances integration, reduces the overall size of the semiconductor device, and lowers manufacturing costs by enabling efficient programming and fault tolerance through the formation of conductive filaments in the anti-fuse structure.
Implementation Method 1
the programming mechanism in the anti-fuse structure creates a short circuit or a relatively low resistance link therein
Data Source
AI summary
The present disclosure provides a semiconductor device with an anti-fuse and a metal-insulator-metal (MIM) capacitor connected to a redistribution layer (RDL) and a method for forming the semiconductor device. The semiconductor device includes a first conductive portion and a second conductive portion disposed over a semiconductor substrate. The semiconductor device also includes a passivation layer covering the first conductive portion and the second conductive portion. The first conductive portion, the second conductive portion and a portion of the passivation layer therebetween form an anti-fuse. The semiconductor device further includes a first metal-insulator-metal (MIM) capacitor and a first redistribution layer (RDL) disposed over the passivation layer. The first MIM capacitor and the first RDL are electrically connected to the first conductive portion, and a first metal layer of the first MIM capacitor is integrally formed with the first RDL.