Antifuse Cell With Opposite-Side Transistors on Shared Semiconductor Layer
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Solution Overview
Problem
Conventional antifuse cells require significant semiconductor substrate area due to the need for multiple transistors and connection regions, and alternative designs that reduce area requirements often incur increased manufacturing complexity and costs by using different gate oxide thicknesses, which can lead to larger transistors and additional manufacturing steps.
Innovation Solution
A semiconductor structure where the program and select transistors share a common semiconductor layer, with their gates positioned on opposite sides, allowing for the elimination of intermediate connection regions and the use of standard manufacturing technologies, such as SOI or Finfets, while concentrating the electric field to reduce programming voltage and area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two transistors are placed next to each other with multiple connection regions, then the antifuse cell can be implemented with conventional structure, but the area occupied on the semiconductor substrate increases significantly
Solution Approach 1:
The patent places the select transistor on the opposite side of the semiconductor substrate relative to the program transistor, utilizing the vertical dimension and substrate thickness to reduce lateral area requirements. This allows the transistors to be stacked rather than placed side-by-side, significantly reducing the footprint of the antifuse cell while maintaining conventional manufacturing processes.
2Area of stationary object
If transistors are placed next to each other without intermediate connection regions to reduce area, then area is reduced, but high voltage damages the gate oxide of the select transistor and thicker gate oxide is required
Solution Approach 1:
By positioning the select transistor on the opposite side of the substrate, the patent eliminates the need for intermediate connection regions between transistors. The electrical connection is achieved through the substrate itself, allowing both transistors to use the same gate oxide thickness and avoiding the need for additional manufacturing steps to create different oxide layers.
Solution Approach 2:
The semiconductor substrate acts as an intermediary, providing both the mechanical support and the electrical connection path between the program transistor and select transistor. This eliminates the need for separate connection regions and allows direct coupling of the transistors without exposing the select transistor gate oxide to damaging high voltages.
3Reliability
If thicker gate oxide is used for select transistor to prevent damage, then the select transistor cannot be realized with minimum feature pitch and becomes larger
Solution Approach 1:
The patent resolves this contradiction by moving the select transistor to the opposite side of the substrate, allowing it to maintain minimum feature pitch and small size while using the same gate oxide thickness as the program transistor. The substrate separation prevents high voltage damage without requiring thicker oxide or larger transistor dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the area occupied by antifuse cells, simplifies manufacturing, and lowers the programming voltage, achieving efficient and cost-effective implementation of antifuse cells with reduced transistor size and shared select transistors for multiple program transistors.
Implementation Method 1
concentrating the electric field to reduce programming voltage and area usage
Implementation Method 2
by applying a high voltage between the two electrodes, a layer of insulator is broken and connection between the electrodes is achieved
Data Source
AI summary
The disclosure relates to a semiconductor structure comprising: a first semiconductor layer, a first program transistor, and a first select transistor implementing a first antifuse cell, wherein the first semiconductor layer acts as the body of the first program transistor and as the body of the first select transistor, wherein a gate of the first program transistor and a gate of the first select transistor are on different sides of the first semiconductor layer.