Anti-fuse OTP Memory Cell Array Without Selection Transistors
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Solution Overview
Problem
Current anti-fuse type one-time programmable (OTP) memory devices face challenges in reducing the planar area occupied, which limits the integration density of semiconductor memory devices, as they typically require selection transistors for programming and reading operations.
Innovation Solution
The anti-fuse type OTP memory cell array is designed without selection transistors, utilizing a metal-oxide-semiconductor (MOS) transistor structure for each unit cell, allowing for selective programming and reading while reducing the planar area, thereby increasing integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If selection transistors are used in anti-fuse type OTP memory cells, then programming and reading operations can be performed, but the planar area occupied increases
Solution Approach 1:
The patent extracts and removes the selection transistors from the memory cell structure, retaining only the essential anti-fuse transistor for storage functionality. This eliminates unnecessary components that consume planar area while maintaining the core programming and reading capabilities through direct word line and bit line connections to the anti-fuse transistor gates and drains.
Solution Approach 2:
The anti-fuse transistor itself performs the selection function that would otherwise require separate selection transistors. By utilizing the inherent characteristics of the anti-fuse structure and appropriate voltage application to its gate, the device enables selective programming and reading operations without requiring additional transistors for cell selection.
2Ease of operation
If selection transistors are included in each unit cell, then selective access is enabled, but integration density decreases
Solution Approach 1:
The patent removes selection transistors from each unit cell, reducing the number of components per cell. This extraction of non-essential elements directly increases the quantity of cells that can be integrated in a given area, thereby improving integration density while maintaining selective access through simplified voltage-controlled mechanisms.
Solution Approach 2:
The patent combines the selection function with the anti-fuse transistor itself, merging what were previously separate functions (selection transistor + anti-fuse transistor) into a single integrated structure. This merging eliminates redundant components and increases the number of unit cells that can be packed into the same area.
Data Source
AI summary
An anti-fuse type one-time programmable (OTP) memory cell array includes a plurality of unit cells which are respectively located at cross points of a plurality of rows and a plurality of columns, a well region shared by the plurality of unit cells, a plurality of anti-fuse gates respectively disposed in the plurality of columns to intersect the well region, a plurality of source/drain regions respectively disposed in portions of the well region between the plurality of anti-fuse gates, and a plurality of drain regions respectively disposed in portions of the well region located at one sides of the anti-fuse gates arrayed in a last column, which are opposite to the anti-fuse gates arrayed in a first column. Each of the unit cells includes one anti-fuse transistor having a MOS transistor structure without a selection transistor.