Antifuse OTP Memory Cell Layout for Higher Integration Density
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Solution Overview
Problem
Current One Time Programmable (OTP) memory devices face challenges such as large memory cell area, low integration degree, complex manufacturing processes, and high manufacturing costs due to their structure, which is similar to Dynamic Random Access Memory (DRAM) with a 1T1C configuration.
Innovation Solution
A semiconductor structure is proposed, featuring a substrate with first and second gate structures of equal thickness, forming a selection transistor and an antifuse bit structure respectively. The antifuse bit structure's breakdown state and non-breakdown state represent different stored data, allowing for efficient data storage in a reduced area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a 1T1C structure similar to DRAM is used for OTP memory, then the memory can be manufactured using existing DRAM processes, but the memory cell occupies a large area and has low integration degree
Solution Approach 1:
The invention extracts and removes the capacitor component from the traditional 1T1C structure, transforming it into a 1T0C structure where data is stored through dielectric breakdown in the capacitor isolation layer rather than through charge storage in a capacitor. This eliminates the need for a separate capacitor structure, thereby reducing the memory cell area while maintaining manufacturability through existing CMOS processes.
Solution Approach 2:
The invention changes the data storage mechanism from three-dimensional charge storage in a capacitor to a two-dimensional dielectric breakdown state in the capacitor isolation layer. This dimensional change allows for more compact memory cell design while simplifying the manufacturing process by eliminating the need for separate capacitor formation steps.
2Reliability
If a 1T1C structure with capacitor is used, then data can be stored using charge storage mechanism, but the manufacturing process becomes complex and manufacturing cost increases
Solution Approach 1:
The invention extracts the capacitor component from the memory cell structure, eliminating the need for complex capacitor formation, insulation layer deposition, and electrode patterning steps. The data storage function is achieved through dielectric breakdown in the existing capacitor isolation layer, which simplifies the manufacturing process while maintaining reliable one-time programmable data storage capability.
Solution Approach 2:
The capacitor isolation layer serves dual functions: it provides electrical isolation between capacitors in adjacent memory cells and simultaneously serves as the storage element for data through dielectric breakdown. This multi-functionality reduces the number of manufacturing steps and simplifies the overall process while maintaining data storage reliability.
3Adaptability or versatility
If traditional 1T1C OTP memory structure is used, then one-time programming functionality is achieved, but the integration degree remains low and area consumption is high
Solution Approach 1:
The invention removes the capacitor structure from the memory cell, transforming the 1T1C configuration into a 1T0C configuration. The one-time programming capability is maintained through dielectric breakdown in the capacitor isolation layer, while the memory cell area is significantly reduced by eliminating the capacitor's physical structure and associated routing.
Solution Approach 2:
The invention merges the isolation function and data storage function into a single component - the capacitor isolation layer. This layer simultaneously provides electrical isolation between adjacent memory cells and stores data through controlled dielectric breakdown, thereby reducing the overall memory cell area while maintaining one-time programming versatility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces the occupied area of the semiconductor structure, improves integration density, simplifies the manufacturing process, and lowers costs by using thin gate oxide structures and overlapping gate structures to minimize area usage and enhance data storage efficiency.
Implementation Method 1
the antifuse bit structure's breakdown state and non-breakdown state represent different stored data
Data Source
AI summary
Disclosed are a semiconductor structure, a memory and a method for operating the memory. The semiconductor structure includes: a substrate; a first gate structure and a second gate structure that are located on a surface of the substrate and have a same thickness smaller than a preset thickness; and a first doped area and a second doped area that are located in the substrate and are respectively located on two sides of the first gate structure. The first gate structure forms a selection transistor with the first and second doped areas; an orthographic projection of the second gate structure on the substrate is at least partially overlapped with the second doped area. The second gate structure and the second doped area form an antifuse bit structure. A breakdown state and a non-breakdown state of the antifuse bit structure are configured to represent different stored data.