Antifuse OTP Memory Cell Layout for Unclonable PUF Code Generation
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Solution Overview
Problem
Current memory technologies lack effective methods for generating unique, unclonable random codes for secure semiconductor chip identification, particularly in high-security applications, due to limitations in manufacturing variations and data protection.
Innovation Solution
A one-time programming memory cell and memory array utilizing antifuse transistors with varying gate oxide layers, where programming and reading voltages are applied to change and determine the storing states, generating random codes based on manufacturing variations for physically unclonable function (PUF) technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory technologies are used, then data storage is achieved, but unique unclonable random code generation for high-security identification is not possible
Solution Approach 1:
The patent utilizes manufacturing process parameters (oxide layer thickness, doping concentrations) to create inherent physical variations in antifuse transistors. These parameter variations at the device level result in unique threshold voltages and conduction characteristics that form the basis of unclonable random codes, transforming conventional memory parameters into security features.
Solution Approach 2:
The system leverages the natural manufacturing variations that inherently exist in semiconductor fabrication processes. Instead of requiring additional security components or complex algorithms, the memory cells themselves provide the random code generation capability through their inherent physical differences, making each chip self-identifying and unclonable.
2Adaptability or versatility
If manufacturing variations are utilized for random code generation, then unique identification is achieved, but precision and control in memory operation are reduced
Solution Approach 1:
The patent converts the harmful effect of manufacturing variations (which typically degrade memory performance and reliability) into a beneficial security feature. The uncontrolled process variations that create yield issues are harnessed to generate unique random codes, transforming a manufacturing defect into a security asset that cannot be replicated.
Solution Approach 2:
The invention applies different operational modes to different aspects of the memory cell. Standard precision control is maintained for basic read/write operations, while the random code generation function deliberately exploits local variations in specific transistor parameters (oxide thickness, doping) to create unique identification patterns.
3Reliability
If antifuse transistors with varying gate oxide layers are used, then unclonable random codes are generated, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent makes the antifuse transistor structure serve multiple functions: standard memory storage operations and unique random code generation. By designing the transistor with variable gate oxide layers that can be controlled during fabrication, the same device structure provides both conventional memory functionality and security identification, eliminating the need for separate security components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the generation of unique random codes for secure semiconductor chip identification, leveraging manufacturing variations to ensure unclonability and enhance security in high-security applications.
Implementation Method 1
a first antifuse transistor... a second antifuse transistor... a storing state of the first antifuse transistor or the second antifuse transistor is changed
Data Source
AI summary
A one time programming memory cell includes a selecting circuit, a first antifuse storing circuit and a second antifuse storing circuit. The selecting circuit is connected with a bit line and a word line. The first antifuse storing circuit is connected between a first antifuse control line and the selecting circuit. The second antifuse storing circuit is connected between a second antifuse control line and the selecting circuit.