Anti-Fuse OTP Memory Layout for Reliable Read Current Detection
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Solution Overview
Problem
Existing one-time-programmable (OTP) memory devices face challenges in ensuring reliable detection of current through dielectric layers in anti-fuse structures due to suboptimal conductive connections, affecting the sensitivity and reliability of sense amplifiers in determining the stored logic values.
Innovation Solution
Improving the conductive connections between word programming lines and anti-fuse structures, as well as between read transistors and bit conducting lines, enhances the sensitivity and reliability of sense amplifiers by optimizing the layout design of memory devices, including the use of conductive via-connectors and conducting lines to facilitate better current detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional layout design is used in OTP memory devices, then manufacturing is simpler, but the conductive connections between word programming lines and anti-fuse structures are suboptimal, reducing sense amplifier reliability
Solution Approach 1:
The patent segments the connection path between word programming lines and anti-fuse structures by introducing intermediate conductive elements (via-connectors and conducting lines). This segmentation allows optimization of each segment's conductive properties, improving overall connection reliability while managing complexity through modular design.
Solution Approach 2:
The patent introduces intermediary conductive structures (via-connectors and conducting lines) that mediate the connection between word programming lines and anti-fuse structures. These intermediaries provide optimized conductive pathways, enhancing signal detection reliability without requiring complete redesign of the entire memory architecture.
2Measurement precision
If conventional layout design is used in OTP memory devices, then device structure is simpler, but current detection sensitivity is reduced
Solution Approach 1:
The patent applies local quality optimization by enhancing conductive connections specifically at critical detection points (between read transistors and bit conducting lines, and between word programming lines and anti-fuse structures). This localized enhancement of conductive quality improves current detection sensitivity without requiring uniform complexity increases throughout the entire device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The improved conductive connections in the layout design of OTP memory devices enhance the sensitivity and reliability of sense amplifiers, enabling accurate detection of current through dielectric layers, thereby improving the overall performance and reliability of the memory device.
Implementation Method 1
a programming electric field is applied across the dielectric material layer to sustainably alter (e.g., break down) the dielectric material, thus decreasing the resistance of the dielectric material layer
Implementation Method 2
a read voltage is applied across the dielectric material layer and a resultant current is read
Data Source
AI summary
A method of making a memory device includes forming an array of memory cells distributed along a first direction and a second direction perpendicular to the first direction, forming a first programming gate-strip extending in the second direction, and forming a plurality of first programming conducting lines extending in the first direction. Each of the memory cells includes an anti-fuse structure having a dielectric layer overlaying a semiconductor region in an active zone, and a transistor having a channel region in the active zone. The active zone extends in the first direction. Each of the plurality of first programming conducting lines is electrically connected connected to the first programming gate-strip through a corresponding resistor of a first plurality of resistors. The first programming gate-strip electrically connects to the anti-fuse structure of each of the memory cells along a column of the array of memory cells.