Antifuse Element With Overlapping Area Ratio For Low Voltage Programming
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Solution Overview
Problem
Conventional antifuse elements in integrated circuits require complex structures, high current density, and high electric fields for programming, which are undesirable as they occupy large footprints and are not suitable for the decreasing size and increasing density of integrated circuits.
Innovation Solution
An antifuse element with a simplified configuration comprising a conductive region in a semiconductor substrate, a dielectric layer, and conductive plugs and members, where the conductive members intersect the conductive region and dielectric layer with a specific overlapping area ratio, allowing programming with a reduced voltage and electro-migration to form conductive filaments, creating a short circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional transistor structure antifuse is used, then programming can be achieved through snap-back breakdown, but the structure becomes complex and occupies large footprint area
Solution Approach 1:
The patent extracts the essential programming function from the complex transistor structure by using a simplified planar configuration with separate conductive plugs and conductive members. The programming capability is achieved through electro-migration and dielectric breakdown in a reduced structure, removing unnecessary transistor components while retaining the core antifuse functionality.
Solution Approach 2:
The patent transitions from a three-dimensional transistor structure to a two-dimensional planar configuration. The conductive plugs and conductive members are arranged in a planar layout with defined overlapping areas, reducing vertical complexity while maintaining programming functionality through lateral field distribution.
2Reliability
If conventional transistor structure antifuse is used, then programming can be achieved, but the footprint area occupied is large which is unsuitable for decreasing IC sizes
Solution Approach 1:
The patent segments the antifuse structure into distinct functional components: conductive plugs formed in the substrate, dielectric layer, and conductive members formed over the plugs. This segmentation allows optimized spacing and overlapping areas, reducing the total footprint while maintaining effective programming through controlled electric fields between segmented elements.
Solution Approach 2:
The patent uses a planar two-dimensional arrangement with conductive members extending in directions perpendicular to the conductive regions, optimizing space utilization. The overlapping area ratio control in the planar configuration reduces footprint compared to vertical transistor structures while maintaining programming effectiveness.
3Reliability
If high current density and high electric field are applied for programming, then dielectric breakdown can be achieved, but the requirements are not suitable for decreasing device sizes
Solution Approach 1:
The patent creates localized high electric field regions at the intersections where conductive members overlap with conductive plugs and dielectric layer. By concentrating the field in specific localized areas with controlled overlapping ratios, the patent achieves dielectric breakdown at lower overall voltage and current levels, enabling scalability to smaller device sizes while maintaining reliable programming capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables programming with lower voltages and reduced footprint, making it suitable for smaller integrated circuits, while maintaining the ability to change digital bit patterns for data storage.
Implementation Method 1
allowing programming with a reduced voltage and electro-migration to form conductive filaments
Implementation Method 2
creating a short circuit
Data Source
AI summary
An antifuse element for an integrated circuit is provided, including a conductive region formed in a semiconductor substrate, extending along a first direction; a dielectric layer formed on a portion of the conductive region; a first conductive plug formed on the dielectric layer; a second conductive plug formed on another portion of the conductive region; and a first conductive member formed over the first and second conductive plugs, extending along a second direction perpendicular to the first direction; and a second conductive member formed over the second conductive plug extending along the second direction, wherein the first conductive member intersects with the conductive region, having a first overlapping area therebetween, and the dielectric layer and the conductive region have a second overlapping area therebetween, and a ratio between the first overlapping area and the second overlapping area is about 1.5:1 to 3:1.