Single Anti-Fuse PUF Cell for Inspection-Resistant Secret Bits
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Solution Overview
Problem
Existing physically unclonable function (PUF) units are susceptible to security vulnerabilities, particularly through passive voltage contrast inspection and electron beam scanning, which can reveal secret bit information stored in floating gate technologies.
Innovation Solution
A PUF unit is designed using a single anti-fuse transistor with a differential sensing circuit and control circuit, where an enroll voltage creates a rupture path on the anti-fuse transistor during the enroll operation, making it difficult for adversaries to distinguish the oxide rupture path and retrieve secret bit information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If floating gate technology is used to store secret bit information in PUF units, then the information can be stored and retrieved, but the security is compromised due to vulnerability to passive voltage contrast inspection and electron beam scanning
Solution Approach 1:
The invention extracts the secret bit information storage function from the floating gate technology and relocates it to the oxide rupture path configuration in the anti-fuse transistor. This separation removes the vulnerability associated with floating gate inspection while preserving the information storage capability.
Solution Approach 2:
The invention changes the physical parameter used for information storage from the electrical charge state of floating gates to the topological configuration of oxide rupture paths. This parameter change fundamentally alters the detectability of the stored information, making it resistant to voltage contrast inspection and electron beam scanning.
2Device complexity
If a single anti-fuse transistor is used instead of traditional PUF structures, then the device complexity is reduced, but the security against hacking must be maintained
Solution Approach 1:
The invention merges multiple functions into the single anti-fuse transistor structure: the information storage function, the security function, and the sensing function. This consolidation reduces device complexity while maintaining security through the inherent properties of the oxide rupture path configuration.
3Reliability
If oxide rupture paths are created in anti-fuse transistor to store entropy bits, then security is enhanced against inspection attacks, but the manufacturing precision requirements increase
Solution Approach 1:
The invention employs self-service by utilizing the natural variability in oxide rupture path formation during manufacturing. The exact configuration of rupture paths is determined by intrinsic material properties and local defects rather than precise manufacturing control, converting a potential manufacturing challenge into a security feature.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the security of entropy bits by making it harder to hack using voltage contrast inspection and electron beam scanning, ensuring the bits are generated and stored in a more secure manner.
Implementation Method 1
the enroll voltage is high enough to create a rupture path on the gate terminal to the first terminal or to the second terminal
Data Source
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AI summary
A physically unclonable function unit (100) includes and anti-fuse transistor (110) and a control circuit (120). The anti-fuse transistor (110) has a first terminal, a second terminal, and a gate terminal. The control circuit (120) is coupled to the anti-fuse transistor (110). During an enroll operation, the control circuit (120) applies an enroll voltage (VP) to the gate terminal of the anti-fuse transistor (110) and applies a reference voltage (V0) to the first terminal and the second terminal of the anti-fuse transistor (110). The enroll voltage (VP) is higher than the reference voltage (V0), and is high enough to create a rupture path on the gate terminal to the first terminal or to the second terminal.