Anti-Fuse Memory Read Path Layout for Low-Resistance Sensing

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Solution Overview

Problem

The existing one-time-programmable (OTP) memory devices face challenges in improving the sensitivity and reliability of detecting the current passing through the dielectric layer of anti-fuse structures during the read operation, due to suboptimal conductive connections between the word programming line and the gate of the anti-fuse structure, and between the second semiconductor terminal of the read transistor and the bit conducting line.

Innovation Solution

The proposed solution involves enhancing the conductive connections by using multiple programming conducting lines and optimized via-connectors to reduce the resistive value between the word programming line and the gate of the anti-fuse structure, and between the source terminal of the read transistor and the sense amplifier, thereby improving the sensitivity and reliability of current detection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple programming conducting lines and optimized via-connectors are used to reduce resistive value, then sensitivity and reliability of current detection is improved, but device complexity increases

Engineering Contradiction:
Improvereliability of current detectionVSAvoidcomplexity of conductive connection structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The conductive connection structure is segmented into multiple programming conducting lines (first programming conducting line, second programming conducting line) and multiple via-connectors (first via-connector, second via-connector). This segmentation allows the current path to be divided into parallel conductive paths, reducing the overall resistive value and improving current detection reliability while distributing the complexity across standardized modular components.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple programming conducting lines and via-connectors are merged to form a composite conductive connection structure. The first and second programming conducting lines are combined with their respective via-connectors to create redundant parallel paths between the word programming line and the bit conducting line, reducing equivalent resistance and improving detection reliability.

Inventive Principle:
Principle #5Merging (Combining)

2Measurement precision

If resistive value between word programming line and gate of anti-fuse structure is reduced, then sensitivity of sense amplifier is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvesensitivity of sense amplifierVSAvoidease of manufacturing conductive connections
Core Design Contradiction:
Measurement precisionVSEase of manufacture

Solution Approach 1:

The connection between the word programming line and the gate of the anti-fuse structure is segmented into multiple discrete conductive elements (programming conducting lines and via-connectors). This segmentation enables parallel current paths that reduce equivalent resistance, improving sense amplifier sensitivity while allowing each individual element to be manufactured using standard processes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Via-connectors are introduced as intermediary elements that bridge the programming conducting lines and the anti-fuse structure gate. These via-connectors serve as mediators that facilitate low-resistance electrical connection while being manufacturable using standard semiconductor fabrication processes, thus improving sensitivity without excessive manufacturing complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If resistive value between source terminal of read transistor and sense amplifier is reduced, then reliability of data reading is improved, but device complexity increases

Engineering Contradiction:
Improvereliability of data readingVSAvoidcomplexity of conductive connection structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The conductive path from the source terminal of the read transistor to the sense amplifier is segmented into multiple programming conducting lines and via-connectors arranged in parallel. This segmentation creates multiple current paths that reduce the equivalent resistance, improving data reading reliability while distributing the structural complexity across standardized components.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple programming conducting lines and via-connectors are merged to form a composite low-resistance connection structure between the read transistor and sense amplifier. The parallel combination of these conductive elements reduces the overall resistive value, improving reliability while using modular components that can be integrated using standard fabrication processes.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the sensitivity and reliability of the sense amplifier to accurately determine the stored logic value by reducing the resistive values of the equivalent resistors, leading to improved performance in reading the stored data in OTP memory devices.

Implementation Method 1

a programming electric field is applied across the dielectric material layer to sustainably alter (e.g., break down) the dielectric material, thus decreasing the resistance of the dielectric material layer

Methodology Applied
Scientific EffectDielectric breakdown: Avalanche Breakdown

Data Source

PatentUS12193223B2Memory device with improved anti-fuse read current
Publication Date: 2025.01.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12193223B2 patent drawing
  • US12193223B2 patent drawing
  • US12193223B2 patent drawing

AI summary

A memory device includes a first programming gate-strip for a first anti-fuse structure and a second programming gate-strip for a second anti-fuse structure. In the memory device, a terminal conductor overlies a terminal region between the channel regions of a first transistor and a second transistor. The memory device also includes a group of first programming conducting and a group of second programming conducting lines. The first programming conducting lines are conductively connected to the first programming gate-strip through a first group of one or more gate via-connectors. The second programming conducting lines are conductively connected to the second programming gate-strip through a second group of one or more gate via-connectors.