Anti-Fuse Serial Number Generator Using CMOS Logic Process
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Solution Overview
Problem
Current methods for incorporating a serial number in integrated circuits as a security feature using non-volatile memory cells are expensive and require substantial process modifications and external equipment, such as laser writers, making them inefficient and costly.
Innovation Solution
An anti-fuse based non-volatile memory device is fabricated using a conventional CMOS logic process, which integrates a sense transistor with the anti-fuse device, allowing for programming without on-chip high voltage circuits and specialized equipment, and is compatible with existing technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional non-volatile memory cells are used to implement serial number feature, then security function is achieved, but manufacturing cost increases and process complexity increases
Solution Approach 1:
The patent combines the serial number storage function with the existing CMOS logic fabrication process by integrating anti-fuse structures during standard manufacturing steps. The anti-fuse devices are formed using the same polysilicon gate, gate dielectric, and doping processes already required for the logic circuits, eliminating the need for separate memory cell fabrication and reducing overall manufacturing cost.
Solution Approach 2:
The invention makes the existing CMOS fabrication process serve multiple functions: it simultaneously creates both the logic circuits and the anti-fuse serial number storage structures. The same process steps (polysilicon deposition, gate dielectric formation, ion implantation) are used for both logic transistors and anti-fuse devices, making the manufacturing process universal and eliminating additional equipment requirements.
2Reliability
If conventional non-volatile memory cells are used to implement serial number feature, then security function is achieved, but process complexity increases due to new process steps and circuits
Solution Approach 1:
The patent merges the anti-fuse structure formation with existing CMOS logic process steps. The polysilicon gate layer serves as both the gate for logic transistors and the electrode for anti-fuse devices. The gate dielectric layer serves as both the gate oxide for logic devices and the dielectric layer for anti-fuse structures. This merging eliminates the need for separate process steps and reduces process complexity.
Solution Approach 2:
The existing CMOS fabrication process serves itself by simultaneously creating both logic circuits and anti-fuse serial number structures without requiring additional specialized equipment or processes. The standard ion implantation, deposition, and etching steps automatically create both device types when appropriately patterned, allowing the process to serve multiple purposes without external assistance.
3Ease of operation
If laser fuse devices are used to implement serial number feature, then programming capability is achieved, but manufacturing cost increases due to substantial process modification and external equipment
Solution Approach 1:
The patent replaces the mechanical/laser-based fuse breaking process with an electrical field-based anti-fuse mechanism. Instead of using external laser equipment to physically break fuses, the invention uses high-voltage electrical fields applied during standard ion implantation to create conductive paths through the gate dielectric, forming anti-fuse structures that can be programmed using existing electrical equipment.
Solution Approach 2:
The patent introduces the gate dielectric layer as an intermediary medium that enables programming capability through standard CMOS processes. This dielectric layer can be broken down by high-voltage stress during ion implantation to create conductive paths, serving as the intermediary between the electrical programming signal and the permanent storage state, eliminating the need for external laser equipment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient and cost-effective fabrication of integrated circuits with embedded serial numbers, reducing the need for additional process steps and equipment, thus lowering production costs and increasing output without compromising complexity or performance.
Implementation Method 1
A gate dielectric layer is formed over the substrate and the well region... The gate dielectric layer is configured to have a breakdown voltage higher than a predetermined voltage
Implementation Method 2
The first contact region is configured to be programmed by applying a high voltage to the first contact region
Data Source
AI summary
An anti-fuse apparatus includes a substrate of a first conductivity type and a well region of a second conductivity type formed in the substrate. A junction between the well region and the substrate is characterized by a breakdown voltage higher than a predetermined voltage. The apparatus includes a contact region of the second conductivity type within the well region. The apparatus also includes a channel region and a drain region within the substrate. A gate dielectric layer overlies the channel region and the contact region. A first polysilicon gate, the drain region, and the well region are associated with an MOS transistor. The apparatus also includes a second polysilicon gate overlying the gate dielectric layer which overlies the contact region. The contact region is configured to receive a first supply voltage and the second polysilicon gate is configured to receive a second supply voltage.