Anti-Fuse Stepped Gate Structure for Controlled Dielectric Breakdown
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Solution Overview
Problem
Existing anti-fuse bitcells in integrated circuits exhibit inconsistent and unpredictable gate dielectric breakdown, leading to reliability concerns and programming disturbances, particularly due to the lack of controlled dielectric breakdown locations and the need for additional masking and patterning techniques.
Innovation Solution
The integration of a select transistor and a split channel transistor with a stepped gate structure, where the stepped gate is thicker than the anti-fuse dielectric layer, to control dielectric breakdown predictably and avoid soft breakdown at the corner of the anti-fuse dielectric layer, thereby isolating dielectric breakdown to the anti-fuse dielectric layer and preventing programming disturbances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing 2T anti-fuse bitcells are used, then the device can be programmed, but gate dielectric breakdown occurs at multiple unpredictable locations leading to large tail in current distribution and reliability concerns
Solution Approach 1:
The channel of the anti-fuse transistor is segmented into two distinct regions: a first channel region with a first gate dielectric layer and a second channel region with a second gate dielectric layer of different thickness. This segmentation ensures that dielectric breakdown occurs predictably at the junction between the two regions rather than at multiple random locations, thereby improving reliability and breakdown location control.
Solution Approach 2:
Different regions of the anti-fuse transistor channel are given different local qualities through varying gate dielectric layer thicknesses. The first channel region has a thicker gate dielectric layer while the second channel region has a thinner gate dielectric layer, creating a controlled gradient that directs breakdown to occur at the interface between these regions with different dielectric properties.
2Reliability
If split channel 1T anti-fuse bitcells with thickness gradient are used, then gate oxide breakdown occurs at the weakest link, but programming disturbances still occur during programming of other AF bitcells
Solution Approach 1:
The anti-fuse transistor is segmented into distinct channel regions with different gate dielectric thicknesses, creating clear spatial separation between the programming path and the read path. This segmentation isolates programming disturbances to specific regions while maintaining overall device functionality, preventing disturbances from affecting other anti-fuse bitcells.
Solution Approach 2:
The stepped gate structure with varying dielectric thicknesses acts as an intermediary element that controls and localizes the high-stress programming voltage. The intermediate region with transitioning dielectric thickness mediates the breakdown process, confining it to a specific location and preventing propagation of programming disturbances to adjacent devices.
3Manufacturing precision
If additional masking and patterning techniques are used to control breakdown, then breakdown location can be controlled, but fabrication complexity and cost increase
Solution Approach 1:
The stepped gate structure is formed by merging multiple gate dielectric layers of different thicknesses into a single integrated structure during the fabrication process. This combining of layers achieves precise breakdown location control through the inherent thickness gradient, eliminating the need for separate masking and patterning steps that would otherwise be required to define the breakdown region.
Solution Approach 2:
The stepped gate structure serves multiple functions simultaneously: it defines the breakdown location, controls the breakdown field distribution, and provides the channel separation all in a single structural element. This multi-functionality achieves precise manufacturing precision without requiring additional fabrication processes for each function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in more robust anti-fuse devices with predictable gate dielectric breakdown, enhancing reliability and avoiding the need for additional masking and patterning techniques, thus improving the robustness and controllability of gate dielectric breakdown within existing fabrication schemes.
Implementation Method 1
When a large programming voltage is applied along the gate of the AF transistor, gate dielectric breakdown occurs and a resistive path is created
Implementation Method 2
When a large programming voltage is applied along the gate of the AF transistor, gate dielectric breakdown occurs
Data Source
AI summary
Integrated circuits and methods of forming the same are provided. An exemplary integrated circuit includes a semiconductor substrate and an anti-fuse device having a select transistor, a bitline contact, and a split channel transistor. The select transistor includes a select gate structure, a bitline source/drain region, and a shared source/drain region. The bitline contact is disposed over and in electrical communication with the bitline source/drain region. The split channel transistor is in electrical communication with the select transistor through the shared source/drain region. The split channel transistor includes an anti-fuse gate structure having an anti-fuse gate and an anti-fuse dielectric layer and a stepped gate structure disposed between the anti-fuse gate structure and the shared source/drain region and having a stepped gate and a stepped dielectric layer. The stepped dielectric layer has a greater thickness than the anti-fuse dielectric layer.