Antifuse Transistor Substrate Potential Control
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Solution Overview
Problem
Existing antifuse transistors require active circuits to be located at a significant distance due to increased substrate potential during programming, leading to high area overhead and risks of parasitic thyristor ignition and thermal destruction.
Innovation Solution
An antifuse transistor with a reduced potential difference between the source and substrate terminals, keeping them at a reference potential, and increasing the drain terminal potential to minimize substrate potential increase, allowing for local thermal heating and formation of a permanent conducting channel without the need for additional process steps or increased safety distances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the substrate potential is raised positively relative to the source potential during programming, then charge carriers are generated in the substrate region enabling current flow, but active circuits in the vicinity cannot be operated and parasitic thyristor may be ignited
Solution Approach 1:
The patent introduces a well region (n-type or p-type) as an intermediary structure between the source and substrate. This well region acts as a mediator that allows the programming current to flow through a controlled path while preventing the substrate potential from rising to harmful levels that would ignite parasitic thyristors or malfunction active circuits. The well region effectively decouples the programming function from the harmful substrate potential effects.
2Object-affected harmful factors
If active circuits are arranged at a considerable distance from the antifuse, then parasitic thyristor ignition is prevented, but area overhead increases
Solution Approach 1:
The well region serves as a localized intermediary structure that can be positioned immediately adjacent to the source and drain, eliminating the need for large safety distances. This intermediary structure contains the programming effects locally, allowing active circuits to be placed much closer to the antifuse structure without risking parasitic thyristor ignition, thereby significantly reducing area overhead.
3Reliability
If additional process steps are implemented to create insulation layers, then electrically programmable antifuse functionality is achieved, but production complexity and costs increase
Solution Approach 1:
The well region structure serves multiple functions: it enables the programming current path, prevents parasitic thyristor ignition, and eliminates the need for additional insulation layers. By making this single structural element multi-functional, the patent achieves the required antifuse programming capability without adding production process complexity or steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables high integration of active circuits with the antifuse, reducing area requirements and preventing parasitic thyristor ignition, thus supporting miniaturization and stable non-volatile storage.
Implementation Method 1
If the current between the source and the drain is selected to be sufficiently high, there will be local thermal heating between the source and the drain until local melting of the semiconductor material occurs
Implementation Method 2
this local thermal heating is of such a magnitude that the semiconductor material melts; a permanent conducting channel is thus being established
Implementation Method 3
charge carriers will be generated in the substrate region (base) across the pn junction between the substrate and the source; by applying a voltage at the drain being positive relative to the source, a current will flow which is generated in the substrate region by the charge carrier injection
Data Source
AI summary
Programmable antifuse transistor, in particular n-channel MOS transistor, and a method for programming at least one such antifuse transistor, includes at least one gate with a gate terminal, source with a source terminal, drain with a drain terminal, and substrate with a substrate terminal, configured so that active circuits/circuit elements do not have to be located at a distance from the antifuse, minimizing area requirements, without additional process steps the level of the potential difference between source terminal and substrate terminal is less than about 0.5 volts, drain terminal and source terminal lie at different potentials. By adjusting drain-source voltage and/or the gate-source voltage a flow of charge carriers occurs between source and drain, causing semiconductor material between source and drain to be thermally heated and to locally melt, forming at least one permanently conducting channel between source and drain.