Anti-Fuse Manufacturing via Tungsten Plug and Metal Etching
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Solution Overview
Problem
Prior art anti-fuse structures and manufacturing methods are not compatible with advanced aluminum backend technology nodes, making it difficult to port integrated circuit device designs from older factories to newer ones using advanced technology, requiring radical redesigns or outdated equipment.
Innovation Solution
A method involving the formation of tungsten plugs in a dielectric layer overlying P and N type silicon, with etched contact openings and a metal layer deposited without liner processing, allowing for the creation of anti-fuse contacts that can be activated by bias voltage to form an electrically conductive path, compatible with 0.35 and 0.25 micron technology nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If prior art anti-fuse structures and methods are used, then compatibility with older technology nodes is maintained, but compatibility with advanced aluminum backend technology nodes (0.35 micron, 0.25 micron) is lost
Solution Approach 1:
The patent changes the metallization process parameters by eliminating the tungsten plug and high-temperature aluminum deposition steps, instead using a standard metal layer deposition followed by etching to form anti-fuse contacts. This parameter change enables compatibility with advanced 0.35 and 0.25 micron technology nodes while simplifying the manufacturing process
Solution Approach 2:
The patent inverts the traditional anti-fuse formation approach by not creating separate contact openings through etching, but instead forming the anti-fuse structure through metal layer deposition and subsequent etching of the metal layer to create contacts. This inversion simplifies the process for advanced technology nodes
2Manufacturing precision
If tungsten etchback process and high temperature aluminum deposition are used, then good contact fill is achieved, but process compatibility with advanced aluminum backend technology is lost
Solution Approach 1:
The patent changes the deposition temperature parameter from high temperature to standard temperature, and eliminates the tungsten plug step entirely. The metal layer is deposited over the tungsten plug and dielectric layer, then etched to form contacts, achieving good contact fill without requiring high-temperature processing compatible only with older technology nodes
Solution Approach 2:
The patent extracts and eliminates the tungsten plug and high-temperature aluminum deposition steps from the process flow, retaining only the essential metal layer deposition and etching steps. This extraction removes the incompatibility with advanced aluminum backend technology while maintaining contact fill quality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the manufacturing of anti-fuse structures compatible with advanced aluminum backend technology nodes, allowing seamless porting of integrated circuit designs without the need for radical redesigns or outdated equipment, and reduces the complexity of the manufacturing process by eliminating the need for salicidation and liner formation.
Implementation Method 1
The dielectric layer is etched to create a first anti-fuse contact opening down to the underlying P type silicon and a second anti-fuse contact opening down to the underlying N type silicon
Implementation Method 2
A metal layer is then deposited over the tungsten plug and over the dielectric layer
Implementation Method 3
The metal layer is then etched to form a first anti-fuse metal contact in the first anti-fuse contact opening and to form a second anti-fuse metal contact in the second anti-fuse contact opening
Implementation Method 4
The application of the bias voltage creates an electrically conductive path from the first anti-fuse metal contact through the underlying P type silicon and through the underlying N type silicon to the second anti-fuse metal contact
Data Source
AI summary
A system and method are disclosed for manufacturing an integrated circuit anti-fuse in conjunction with a tungsten plug process. A tungsten plug is formed in a dielectric layer that overlies a portion of P type silicon and an adjacent portion of N type silicon. The dielectric layer is etched to create a first anti-fuse contact opening down to the underlying P type silicon and a second anti-fuse contact opening down to the underlying N type silicon. A metal layer is deposited over the tungsten plug and over the dielectric layer and etched to form an anti-fuse metal contact in each of two anti-fuse contact openings. A bias voltage is applied to the anti-fuse metal contacts to activate the anti-fuse.