Anti-fuse Device Parallel Transistor Layout for Uniform Field
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Solution Overview
Problem
Existing anti-fuse bit programming and read operations in integrated circuits (ICs) face challenges with non-uniform electric field application and resistance variations, leading to inaccurate detection of programmed status, especially in weakly programmed devices.
Innovation Solution
The use of two selection transistors to couple the anti-fuse device to a bit line, providing parallel current paths and improving electric field uniformity, reduces device resistance variations and enhances current detection accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single transistor couples the anti-fuse device to a bit line, then the device complexity is reduced, but the electric field uniformity deteriorates and measurement precision decreases
Solution Approach 1:
The patent divides the single transistor coupling into two separate transistors (first transistor and second transistor) that couple the anti-fuse device to the bit line through parallel current paths. This segmentation allows independent control of each transistor gate, enabling uniform electric field application across the dielectric material and improving detection accuracy for both strongly and weakly programmed devices.
2Device complexity
If a single transistor couples the anti-fuse device to a bit line, then the device complexity is reduced, but the path resistance increases
Solution Approach 1:
The patent segments the current path into two parallel paths, each controlled by a separate transistor. This creates multiple current paths between the anti-fuse device and the bit line, reducing the overall path resistance and improving current detection reliability through redundant conduction channels.
3Ease of manufacture
If non-uniform electric field is applied across the dielectric material, then the programming process is simpler, but the manufacturing precision deteriorates
Solution Approach 1:
The patent applies equipotentiality by using two transistors with independently controlled gates to create a uniform electric field distribution across the dielectric material layer. By controlling the voltage applied through each transistor gate, the system achieves uniform potential distribution, ensuring consistent dielectric breakdown characteristics across different memory locations during programming.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the accuracy of detecting programmed status by ensuring a more uniform electric field and lower path resistance, improving the detection of both strongly and weakly programmed anti-fuse devices.
Implementation Method 1
a programming electric field is applied across the dielectric material layer to sustainably alter (e.g., break down) the dielectric material, thus decreasing the resistance of the dielectric material layer
Implementation Method 2
The first current path goes through a first portion of the active area and the second current path goes through a second portion of the active area
Data Source
AI summary
A method of manufacturing an anti-fuse device includes forming an anti-fuse structure on a substrate, forming a first transistor at a first position away from the anti-fuse device in a first direction, and forming a second transistor at a second position away from the anti-fuse device in a second direction opposite the first direction. Forming the anti-fuse structure includes forming first and second S/D structures in an active area, the first transistor includes the first S/D structure, and the second transistor includes the second S/D structure. The method includes constructing a first electrical connection between gate structures of the first and second transistors and a second electrical connection between a third S/D structure of the first transistor and a fourth S/D structure of the second transistor.