Antimony-Based III-V FETs Monolithic Integration
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Solution Overview
Problem
The integration of PMOS and NMOS transistors comprising III-V compound semiconductors on a single chip is challenging due to the difficulty in finding materials with satisfactory electron and hole mobilities, and high manufacturing costs.
Innovation Solution
The development of an integrated circuit structure with alternating layers of III-V semiconductor materials, including bottom and top barriers, channel layers, and cap layers, formed through epitaxial growth, which creates quantum wells to enhance electron and hole mobilities, and the use of antimony-based materials to achieve high drive currents for both types of transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If III-V compound semiconductors are used to form NMOS transistors to achieve high electron mobility, then electron mobility is improved, but finding materials with satisfactory hole mobility for PMOS transistors becomes difficult
Solution Approach 1:
The patent employs composite material structures with multiple III-V compound semiconductor layers (e.g., InGaAs, InAlAs, AlInAs) with different compositions and properties. Each layer is optimized for specific functions: high electron mobility channels for NMOS, and layers with appropriate band structures for PMOS operation, achieving both high electron and hole mobilities through material composition design
Solution Approach 2:
Different regions of the semiconductor structure are assigned different material compositions and properties. The channel regions are optimized locally for high carrier mobility, while barrier and contact regions are optimized for their specific functions, allowing simultaneous optimization of electron and hole transport in different parts of the device
2Adaptability or versatility
If methods are developed to form PMOS transistors using III-V compound semiconductors, then PMOS functionality is achieved, but manufacturing costs increase
Solution Approach 1:
The patent combines the formation of NMOS and PMOS transistors into a single integrated process flow using the same III-V compound semiconductor material system. Both types of transistors are fabricated on the same chip using compatible epitaxial growth and processing techniques, eliminating the need for separate material systems and reducing overall manufacturing complexity and cost
Solution Approach 2:
A universal III-V compound semiconductor material platform is developed that can support both NMOS and PMOS transistor fabrication. The same base material system (e.g., InGaAs/InAlAs) is used for both transistor types, with only minor compositional adjustments needed, making the manufacturing process universally applicable to complementary device pairs
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in complementary FETs with high drive currents and balanced performance, reducing manufacturing costs while achieving high electron and hole mobilities, thereby addressing the challenges of integrating PMOS and NMOS transistors on a shared chip.
Implementation Method 1
formed through epitaxial growth, which creates quantum wells to enhance electron and hole mobilities
Data Source
AI summary
An integrated circuit structure includes a substrate and a first and a second plurality of III-V semiconductor layers. The first plurality of III-V semiconductor layers includes a first bottom barrier over the substrate; a first channel layer over the first bottom barrier; and a first top barrier over the first channel layer. A first field-effect transistor (FET) includes a first channel region, which includes a portion of the first channel layer. The second plurality of III-V semiconductor layers is over the first plurality of III-V semiconductor layers and includes a second bottom barrier; a second channel layer over the second bottom barrier; and a second top barrier over the second channel layer. A second FET includes a second channel region, which includes a portion of the second channel layer.