Antimony Ion Implantation for Semiconductor Source/Drain Extensions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor fabrication techniques face challenges in achieving optimal source/drain extension region doping with dopants like arsenic and phosphorus, which often result in conflicting performance metrics such as high sheet resistance and short channel effects, and antimony, while promising, is sensitive to high temperatures, leading to deactivation during thermal annealing.
Innovation Solution
The use of antimony as an n-type dopant with a high-temperature, short-duration anneal to activate and preserve its performance, combined with precise implantation techniques such as amorphization and angular implantation, and the inclusion of a low thermal budget sidewall spacer to prevent deactivation, facilitates the formation of ultra-thin source/drain extension regions with improved conductance and reduced short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional dopants like arsenic and phosphorus are used for source/drain extension region doping, then doping can be achieved, but sheet resistance becomes high and short channel effects occur
Solution Approach 1:
The patent changes the dopant type from conventional arsenic or phosphorus to antimony, which has different atomic properties (larger atomic mass and different diffusion characteristics). This parameter change enables achieving lower sheet resistance and more abrupt junction profiles, thereby improving transistor performance while suppressing short channel effects
2Reliability
If antimony is used as dopant with conventional thermal annealing, then dopant activation can be achieved, but antimony becomes deactivated due to sensitivity to high temperatures
Solution Approach 1:
The patent changes the annealing parameters from conventional high-temperature long-duration thermal annealing to lower-temperature shorter-duration annealing. This parameter modification prevents antimony deactivation while still achieving sufficient dopant activation, resolving the contradiction between activation effectiveness and dopant stability
Solution Approach 2:
The patent performs the antimony doping and activation before subsequent high-temperature processing steps. By completing the antimony activation early in the process sequence, the dopant is already activated and protected from deactivation during later high-temperature steps, eliminating the need for re-activation
3Manufacturing precision
If source/drain extension regions are formed with conventional doping, then regions can be created, but junction gradients are gradual and performance is limited
Solution Approach 1:
The patent utilizes the unique properties of antimony dopant combined with precise ion implantation parameters to achieve more abrupt junction gradients. The antimony dopant's characteristics enable sharper junction profiles compared to conventional dopants, improving manufacturing precision without significantly increasing process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in lower sheet resistance, more abrupt junction gradients, and higher transistor performance by effectively suppressing short channel effects while maintaining antimony's activation, enabling the formation of shallow source/drain regions with desirable electrical characteristics.
Implementation Method 1
implanting an n-type dopant in order to create the electronically active regions
Implementation Method 2
Each dopant is exposed to a thermal anneal, which restores the crystalline lattice structure of the semiconductor wafer and also electronically activates the dopant ions
Data Source
AI summary
A method is disclosed for implanting and activating antimony as a dopant in a semiconductor substrate. A method is also disclosed for implanting and activating antimony to form a source/drain extension region in the formation of a transistor, in such a manner as to achieve high activation and avoid deactivation via subsequent exposure to high temperatures. This technique facilitates the formation of very thin source/drain regions that exhibit reduced sheet resistance while also suppressing short channel effects. Enhancements to these techniques are also suggested for more precise implantation of antimony to create a shallower source/drain extension, and to ensure formation of the source/drain extension region to underlap the gate. Also disclosed are transistors and other semiconductor components that include doped regions comprising activated antimony, such as those formed according to the disclosed methods.