Antiparallel LED and ESD Diode Integration on Single Wafer
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Solution Overview
Problem
The existing methods for producing optoelectronic semiconductor components are not cost-effective, particularly in integrating light-emitting diode chips with ESD protection diodes, which often require additional work steps and result in increased production costs.
Innovation Solution
A method involving the epitaxial deposition of a semiconductor layer stack with a pn junction on a substrate, followed by lateral structuring into pairs of semiconductor bodies, where the substrate is detached, and the bodies are connected antiparallel on a connection carrier, allowing for the simultaneous production of light-emitting diode chips and ESD protection diodes without additional work steps, utilizing a single wafer and reducing material waste.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If light-emitting diode chips and ESD protection diodes are produced separately using existing methods, then each component can be optimized individually, but production costs increase and additional work steps are required
Solution Approach 1:
The patent merges the production of light-emitting diode chips and ESD protection diodes into a single integrated process. Both components are formed on the same semiconductor wafer through shared epitaxial growth and processing steps, eliminating the need for separate production lines and reducing overall manufacturing complexity while lowering costs.
Solution Approach 2:
The semiconductor wafer serves multiple functions simultaneously: it acts as the substrate for both light-emitting diode chips and ESD protection diodes, and the epitaxial growth process produces both component types in parallel. This multi-functional approach allows single wafer to produce multiple product types without additional processing steps.
2Reliability
If additional work steps are added to integrate ESD protection diodes with light-emitting diode chips, then integration is achieved, but production efficiency decreases and costs increase
Solution Approach 1:
The patent performs preliminary structuring of the semiconductor wafer during the epitaxial growth phase, where both light-emitting diode and ESD protection diode structures are formed simultaneously before any separation or individual processing occurs. This preliminary formation of both component types ensures high integration reliability while avoiding subsequent additional work steps that would reduce productivity.
3Reliability
If different thicknesses are used for light-emitting diode chips and ESD protection diodes, then each component can be optimized for its specific function, but manufacturing complexity increases
Solution Approach 1:
The patent applies local quality by forming both light-emitting diode and ESD protection diode structures with identical thickness during epitaxial growth, then using selective etching to remove specific portions. This approach maintains manufacturing simplicity through uniform initial processing while achieving functionally optimized final geometries - light-emitting diodes retain full thickness for optimal light generation, while ESD protection diodes have selectively removed portions for their specific protective function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the cost-effective production of optoelectronic semiconductor components with integrated ESD protection diodes, maintaining the same thickness as light-emitting diode chips, allowing for the use of inexpensive connection carriers and ensuring that ESD protection does not interfere with the testing of light-emitting diode chips.
Implementation Method 1
the semiconductor layer stack is epitaxially deposited on the substrate
Data Source
Figure 1A~1B
Figure 1C~1D
Figure 1E~1F
AI summary
A method for producing an optoelectronic semiconductor component is specified, comprising the following steps: - arranging a semiconductor layer stack (101) having a pn junction (104) on a substrate (100), - laterally structuring the semiconductor layer stack (101) into a multiplicity of pairs of first semiconductor bodies (1) and second semiconductor bodies (2), which are spaced apart from one another in a lateral direction (1), - detaching the substrate (100) from the pairs of first semiconductor bodies (1) and second semiconductor bodies (2), - applying at least one pair of first semiconductor bodies (1) and second semiconductor bodies (2) to a connection carrier (3) having electrical connection locations (4) and/or at least one conductor track (5), - electrically connecting the semiconductor bodies (1) of a pair of first semiconductor bodies (1) and second semiconductor bodies (2) by means of the connection locations (3) and/or the at least one conductor track (4) in such a way that the pn junction (104) of the first semiconductor body (1) is connected in antiparallel with the pn junction (104) of the second semiconductor body (2).