Anti-Phase Asynchronous Clocking for Time-Interleaved SAR ADCs
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Solution Overview
Problem
Analog-to-digital converters (ADCs) face challenges in generating asynchronous clock signals for successive approximation ADC architectures, leading to inefficiencies in comparison cycles and increased power consumption due to kickback noises and comparator reset times.
Innovation Solution
A clock generation circuit that generates anti-phase asynchronous clock signals for time-interleaved comparators, controlled by stop signals from a successive approximation register (SAR) logic circuit, allowing for programmable resolution and reducing power consumption by disabling unused comparators and minimizing stray capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If synchronous clock signals are used for comparators, then clock generation is simple, but kickback noises increase and power consumption rises
Solution Approach 1:
The patent employs periodic anti-phase clock signals to alternately activate two comparators, allowing one comparator to be reset while the other performs comparison. This periodic switching reduces kickback noise and power consumption by ensuring comparators are not simultaneously active, resolving the contradiction between simple clock generation and reduced power loss.
Solution Approach 2:
The patent divides the comparator system into two segments (first and second comparators) that operate in alternating phases. Each comparator is activated by its own dedicated clock signal, segmenting the comparison function to reduce simultaneous kickback noise and lower overall power consumption while maintaining conversion speed.
2Reliability
If comparator reset time is included in clock generation loop, then comparators are properly reset, but SAR conversion cycles increase
Solution Approach 1:
The patent performs comparator reset in advance during the inactive phase of each comparator's operation cycle. By resetting comparators before they are needed for the next comparison, the reset operation does not delay the SAR conversion cycles, thus maintaining high productivity while ensuring reliable comparator reset.
Solution Approach 2:
The patent maintains continuous useful action by overlapping the reset phase of one comparator with the active comparison phase of the other. This continuous operation ensures that comparators are always ready when needed without introducing idle time, thereby maintaining high conversion speed while ensuring proper reset.
3Measurement precision
If all comparators are kept active, then conversion resolution is maintained, but power consumption increases
Solution Approach 1:
The patent uses periodic anti-phase clock signals to alternately activate two comparators, allowing one comparator to be reset while the other performs comparison. This periodic switching reduces kickback noise and power consumption by ensuring comparators are not simultaneously active, resolving the contradiction between simple clock generation and reduced power loss.
Solution Approach 2:
The patent divides the comparator system into two segments (first and second comparators) that operate in alternating phases. Each comparator is activated by its own dedicated clock signal, segmenting the comparison function to reduce simultaneous kickback noise and lower overall power consumption while maintaining conversion speed.
Data Source
AI summary
Apparatus and associated methods relate to a clock generation circuit which generates asynchronous clock signals for a successive approximation ADC architecture based on time-interleaved comparators. In an illustrative example, a circuit may include (a) a first comparator configured to receive an input signal and generate a first ready signal to indicate a comparison decision being complete, (b) a second comparator configured to receive the input signal and generate a second ready signal to indicate a comparison decision being complete, and (c) a clock generation circuit coupled to receive the first and the second ready signals and generate a first clock for the first comparator and a second clock for the second comparator. The first and the second clock signals may be in anti-phase. Thus, each comparator may have enough time to reach a valid comparison in each successive approximation cycle, and kickback noises at comparator' inputs may be advantageously reduced.