Always-On Signal Routing in System-on-Chip Power Management
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Solution Overview
Problem
In System on a Chip (SoC) designs, always-on routing of signals across different power modes is inefficient due to limited chip area and power resources, leading to significant pin routing overhead and challenges in preserving pseudo-static signal states during sleep and wake-up modes.
Innovation Solution
A method and apparatus for saving always-on (AON) routing of signals across chips, involving the use of power signals, clamp keeper cells, and reset signal generation circuits to manage power modes, where a first power signal is turned ON upon asserting a Power ON Reset (PoR) and clamp control signals, and a second power signal is turned ON after the first, with the PoR signal de-asserted once the second power signal is ON, allowing logic signals to be latched and routed across sections while minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If always-on routing is used to preserve signal states across power modes, then signal state preservation is improved, but chip area and power resources are consumed
Solution Approach 1:
The SoC is divided into always-on and non-always-on sections, allowing selective routing. Only critical signals require always-on routing in the first section, while other signals can be routed through the second section when powered on, reducing the overall area dedicated to always-on routing.
Solution Approach 2:
Different routing quality is provided for different signal types and locations. Critical pseudo-static signals receive always-on routing protection in the first section, while other signals use standard routing in the second section, optimizing area usage based on local signal requirements.
2Reliability
If always-on routing is used to preserve signal states across power modes, then signal state preservation is improved, but power consumption increases
Solution Approach 1:
Power consumption is segmented by dividing the routing into always-on and non-always-on sections. Only the essential control signals in the first section consume power continuously, while the majority of signals in the second section can be powered down when not in use, significantly reducing overall power consumption.
Solution Approach 2:
Different power delivery strategies are applied to different signal routes. Critical signals receive continuous power delivery for state preservation, while other signals receive power only when needed, optimizing the balance between reliability and power consumption.
3Device complexity
If pin routing overhead is reduced by minimizing always-on routing, then resource usage is improved, but signal state preservation during sleep/wake-up modes becomes challenging
Solution Approach 1:
The routing is segmented into two sections with different power management strategies. The first section maintains always-on capability for critical signals with minimal pin routing overhead, while the second section handles other signals with standard routing, reducing overall complexity while preserving necessary signal states.
Solution Approach 2:
The system performs preliminary actions by asserting power signals in a specific sequence before mode transitions. Power signals are asserted in advance to ensure critical signals are ready before sleep or wake-up modes, preserving signal states without requiring extensive always-on routing.
Data Source
AI summary
Aspects of the disclosure are directed to saving always on (AON) routing of signals across chips, the disclosure includes turning ON a first power signal in a system on a chip (SOC) when a Power ON Reset (PoR) signal is asserted and a clamp control signal is asserted; turning ON a second power signal in the SOC after the first power signal is turned ON; de-asserting the PoR signal after the second power signal is turned ON; latching a logic signal with a LOW clamp keeper cell if the logic signal is at a LOW logic level or with a HIGH clamp keeper cell if the signal is at a HIGH logic level; and de-asserting the second power signal while a first section of the SOC routes the logic signal through a second section of the SOC.