Shared Memory Segmentation for AP-CP Data Processing Bottlenecks
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Solution Overview
Problem
Current communication devices face limitations in data throughput and processing speed due to the high number of data read/write operations between Application Processors (AP) and Communication Processors (CP) sharing a storage unit, leading to congestion and bottlenecks in Dynamic Memory Controller access, especially as data throughput increases.
Innovation Solution
The proposed solution involves an apparatus and circuit that minimizes data read/write operations by using a shared storage unit with distinct regions for AP and CP data, eliminating the need for external Interface units, and utilizing Direct Memory Access (DMA) and Chip-to-Chip communication to manage data processing between AP and CP, thereby reducing the load on the Dynamic Random Access Memory (DRAM) and enhancing processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transmitted between AP and CP through external Interface units using shared memory, then data communication between processors is enabled, but the number of data read/write operations increases leading to congestion and reduced processing speed
Solution Approach 1:
The shared memory space is segmented into distinct regions: a first memory region allocated exclusively to the AP, a second memory region allocated exclusively to the CP, and a third memory region serving as a communication buffer between them. This segmentation allows each processor to access its dedicated region without causing read/write operations in the other processor's region, thereby reducing memory access congestion while maintaining inter-processor communication capability through the shared third region.
2Productivity
If external Interface units are used for data transmission between AP and CP, then data communication is achieved, but bandwidth limitations and bottlenecks reduce overall data throughput
Solution Approach 1:
The patent merges the memory access paths of AP and CP by allowing both processors to directly access the shared memory space without requiring external Interface units for data transmission. The segmented memory structure enables parallel access to different regions, effectively combining the bandwidth capacity of both processors while eliminating the bottleneck imposed by external Interface units.
3Adaptability or versatility
If multiple processors share a common storage unit, then data exchange between processors is facilitated, but access congestion occurs reducing system performance
Solution Approach 1:
The shared storage unit is divided into multiple independently accessible regions, with each region assigned to specific processors. The AP accesses the first and third regions, while the CP accesses the second and third regions. This spatial segmentation eliminates access conflicts and congestion, allowing simultaneous operations without compromising memory access speed or inter-processor data exchange capability.
Data Source
AI summary
A circuit for processing data is provided. The circuit includes an Application Processor (AP), a Communication Processor (CP), and a storage unit including at least a first region which the AP and the CP access and from/to which data related to at least one of the AP and the CP is read/written, and a second region which the CP accesses and from/to which data related to the CP is read/written.