AP-Pinned Racetrack MTJ Memory for Stable Multi-Bit AI Inference

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Solution Overview

Problem

Challenges in racetrack memory applications include significant demagnetization in the Magnetic Tunnel Junction (MTJ) data storage layer leading to bit degradation, processing and manufacturing difficulties, inefficient spin-orbit torque utilization causing high energy consumption, and low operating temperatures due to low melting points of topological insulator materials, limiting large array production.

Innovation Solution

Implementing an anti-parallel pinned (AP-pinned) storage layer with topological half Heusler alloy (THHA) materials, coupled with doping or cluster co-deposition, and laminated multilayer structures to enhance reliability and thermal stability, while using coherent spin-polarized electrical current for data storage and reading.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If conventional heavy metal materials are used for spin-orbit torque, then data writing is enabled, but energy consumption increases and device reliability decreases

Engineering Contradiction:

Improveenergy consumptionVSAvoiddevice reliability

Core Design Contradiction:

Loss of energyVSReliability

Solution Approach 1:

The patent changes the material parameter from conventional heavy metals to topological insulator materials, which fundamentally alters the spin-orbit coupling mechanism and reduces energy consumption while improving device reliability through enhanced thermal stability

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent employs composite material structures including topological insulator/SOT-MTJ stacks and multi-layered configurations that combine different materials with complementary properties to achieve both low energy consumption and high reliability

Inventive Principle:

Principle #40Composite materials

2Reliability

If topological insulator materials are used in SOT cells, then thermal stability is improved, but operating temperature is limited due to low melting point

Engineering Contradiction:

Improvethermal stabilityVSAvoidoperating temperature

Core Design Contradiction:

ReliabilityVSTemperature

Solution Approach 1:

The patent uses composite material structures including topological insulator/SOT-MTJ stacks and multi-layered configurations that combine different materials with complementary properties to achieve both low energy consumption and high reliability

Inventive Principle:

Principle #40Composite materials

Solution Approach 2:

The patent applies localized material engineering by introducing doping elements at specific positions within the topological insulator lattice to enhance thermal stability without compromising the fundamental topological properties needed for low-energy operation

Inventive Principle:

Principle #3Local quality

3Reliability

If magnetic racetrack storage layer is used, then data storage is enabled, but demagnetization occurs leading to bit degradation and low manufacturing yield

Engineering Contradiction:

Improvelong-term reliabilityVSAvoidmanufacturing yield

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent changes the magnetic anisotropy parameter by introducing doping elements that modify the crystal field and exchange interactions, thereby stabilizing the magnetic moments against demagnetization while maintaining manufacturability

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent applies protective material layers and optimized structural configurations before manufacturing processes that prevent demagnetization effects and bit degradation during fabrication and operation, thereby improving yield and reliability

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enhances long-term reliability and read-back signal-to-noise ratio (SNR) at high temperatures, improving manufacturing yield and reducing costs for AI inference devices.

Implementation Method 1

the magnetic racetrack data storage layer is configured to store multipolar bits through domain walls (DWs) which are driven to move together along the magnetic racetrack data storage layer by pulses of coherent spin-polarized electrical current

Methodology Applied

Scientific EffectSpin-polarized electrical current:

Implementation Method 2

employing the tunneling magnetoresistance (TMR) effect for data reading

Methodology Applied

Scientific EffectTunneling magnetoresistance (TMR) effect: Magnetoresistance

Implementation Method 3

the spin orbit torque (SOT) effect for data writing

Methodology Applied

Scientific EffectSpin orbit torque (SOT) effect:

Data Source

PatentUS20250338504A1Topological Racetrack Memory having Multi-bits Storage Capability Each Unit Cell for In-memory Computing in Artificial Intelligent Inference Device

Publication Date: 2025.10.30 AURORA MICRO DEVICES LLC

AI summary

An apparatus and a fabricating method therefor of magnetic racetrack in-memory computing AI inference chip utilizing magnetic topological spin orbital torque (SOT) magnetic tunnel junction (MTJ) array unit cells comprises a SOT cell having laminated topological half Heusler alloy (THHA) layer, a MTJ cell having AP-pinned racetrack data storage layer, wherein the SOT and the magnetic racetrack data storage layer are configured to generate memory writing, the tunnel magnetoresistive (TMR) MTJ and the magnetic racetrack data storage layer are configured to provide memory reading, the magnetic racetrack data storage layer is configured to store multipolar bits through domain walls (DWs) which are driven to move together along the magnetic racetrack data storage layer by pulses of coherent spin-polarized electrical current, and together the SOT-MTJ cells having multi-bits data storage capability each cell are configuring a non-volatile memory array to store a corresponding programmable weight matrix for AI in-memory computing.