APD Wiring Layout for Breakdown Voltage Stability and Low Dark Count
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Solution Overview
Problem
The existing photoelectric conversion apparatuses face issues with changes in breakdown voltage over time due to hot carrier injection into the semiconductor substrate interface and increased dark count rates (DCR) due to electric field concentration near the guard ring region.
Innovation Solution
The proposed solution involves a photoelectric conversion apparatus with a specific semiconductor layer structure, including avalanche diodes with carefully designed wiring structures and semiconductor regions to manage the electric field and reduce hot carrier trapping, ensuring that the boundary between wiring portions and the insulating film does not overlap the semiconductor regions where hot carriers are generated, thereby stabilizing the breakdown voltage and reducing DCR.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a cathode wire is disposed immediately above a guard ring region to improve photoelectric conversion efficiency, then the optical path length is lengthened and quantum conversion efficiency is improved, but hot carriers are trapped near the cathode region and the breakdown voltage changes over time
Solution Approach 1:
The patent extracts the harmful effect by introducing a dedicated guard ring region that is electrically isolated from the cathode wire. This separate structure absorbs and contains the hot carriers that would otherwise be trapped near the cathode region, preventing them from causing potential changes and breakdown voltage drift over time.
Solution Approach 2:
The guard ring region acts as an intermediary structure between the cathode wire and the semiconductor substrate interface. It mediates the interaction by providing a controlled path for hot carriers to dissipate, thereby protecting the cathode region from hot carrier trapping effects while maintaining the beneficial optical path lengthening.
2Reliability
If an anode wire is disposed immediately above a guard ring region to improve photoelectric conversion efficiency, then the optical path length is lengthened, but electric field concentrates in the end portion of the cathode region and the dark count rate increases
Solution Approach 1:
The patent applies local quality by creating a specific spatial arrangement where the anode wire is positioned at a controlled distance from the guard ring region. This localized configuration optimizes the electric field distribution in different regions: the guard ring region handles hot carrier management while the anode wire maintains photoelectric conversion efficiency, preventing electric field concentration at the cathode region ends.
Solution Approach 2:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional spatial configuration by carefully controlling the vertical and horizontal positions of the anode wire relative to the guard ring region. This dimensional adjustment allows optimization of both photoelectric conversion efficiency and dark count rate by distributing electric field intensity across multiple spatial dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the change in breakdown voltage over time and decreases the dark count rate, enhancing the stability and performance of the photoelectric conversion apparatus.
Implementation Method 1
an avalanche multiplication region between the first semiconductor region and the second semiconductor region
Implementation Method 2
incident light passing through a semiconductor substrate
Data Source
AI summary
A photoelectric conversion apparatus includes an avalanche diode (APD) disposed in a semiconductor layer, and a first wiring structure, the APD including a first semiconductor region disposed at a first depth, a second semiconductor region disposed at a second depth deeper than the first depth, a third semiconductor region disposed in contact with an end portion of the first semiconductor region, a first wiring portion connected to the first semiconductor region, and a second wiring portion connected to the second semiconductor region, wherein a first pad configured to apply a first voltage to the photoelectric conversion apparatus is disposed in the first wiring structure, and wherein in the planar view, at least a part of a boundary portion between an insulating film facing the first wiring portion and the second wiring portion overlaps the third semiconductor region and does not overlap the first semiconductor region.