IC Package System Aperture Leadframe Die Stacking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing integrated circuit packaging methods, such as vertically stacked multi-chip modules, face challenges in increased manufacturing costs, decreased product yield due to extra assembly steps, and limited electrical interconnections and signal routing capabilities, which hinder the efficient use of wafer space and chip density.
Innovation Solution
The integrated circuit package system employs a leadframe with an aperture to mount a known good die package, allowing for independent testing of components before assembly and enabling efficient stacking and modularization of IC components, with wire bonding and molding for enhanced reliability and durability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically stacked MCM assembly is performed before chip testing, then chip density increases, but manufacturing cost increases and product yield decreases
Solution Approach 1:
The patent applies preliminary action by testing and selecting chips before assembly into the MCM structure. Individual chips are pre-tested to identify functional defects, and only known-good chips are selected for assembly. This preliminary screening prevents defective chips from being assembled, thereby maintaining high product yield while achieving high chip density through efficient space utilization.
2Adaptability or versatility
If bottom chip is made larger to accommodate bond pads, then electrical interconnection capability improves, but wafer space utilization decreases
Solution Approach 1:
The patent transitions from two-dimensional horizontal arrangement to three-dimensional vertical stacking. Multiple chips are stacked vertically on the MCM substrate, allowing electrical interconnections to extend through multiple layers via through-substrate vias and vertical conductors. This dimensional change enables sufficient interconnection capability without requiring larger individual chip areas, thereby maximizing wafer space utilization.
Solution Approach 2:
The patent implements nesting by placing smaller chips vertically above larger chips on the MCM substrate. The hierarchical arrangement allows smaller chips to be positioned in the vertical space above the substrate, creating a nested configuration that maximizes the use of available wafer area while providing adequate bond pad areas on each chip for electrical interconnections.
3Device complexity
If simple fan-out interconnection is used, then manufacturing complexity decreases, but signal routing capability is limited
Solution Approach 1:
The patent segments the interconnection system into multiple functional layers: horizontal fan-out interconnections on the substrate plane, vertical through-substrate vias for inter-layer connections, and chip-to-chip vertical interconnections. This segmentation allows the system to maintain manufacturing simplicity through standardized processes while achieving sophisticated signal routing capabilities across multiple dimensions and layers.
Data Source
AI summary
An integrated circuit package system includes providing a leadframe, forming an aperture within the leadframe, mounting an integrated circuit package over or under the aperture, and mounting a die over the integrated circuit package with the die located within the aperture.