Algorithmic Pattern Generator Sub-Instruction Repeats
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Solution Overview
Problem
The increasing complexity and speed of modern integrated circuits and memory devices tax the resources of integrated circuit testers, requiring longer testing times and making it difficult to develop new test patterns and reuse existing ones, especially when transitioning to new designs or speed grades.
Innovation Solution
The use of simplified methods for programming parallel coupled Algorithmic Pattern Generators (APGs) with sub-instruction repeats to generate test vectors and part commands, allowing for easier adjustments in timing and reuse of test code across different part speed grades and designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple parallel APGs are used to test modern integrated circuits, then testing throughput and speed are improved, but device complexity and programming difficulty increase
Solution Approach 1:
The patent segments the test pattern generation into multiple parallel APGs, each handling a portion of the testing workload. This allows the system to maintain high throughput while managing complexity through modular organization of test generation tasks across multiple independent but coordinated generators.
Solution Approach 2:
The patent implements a universal programming interface that allows a single test program to control multiple parallel APGs. This multi-functional interface enables the same programming logic to be applied across different APG instances, reducing the overall programming complexity despite having multiple parallel generators.
2Productivity
If test patterns are developed for parallel APG usage, then testing speed is improved, but the ability to reuse portions of old patterns in new designs is reduced
Solution Approach 1:
The patent creates a universal programming interface that enables test patterns to be written in a standardized format that can be executed by multiple parallel APGs. This universality allows existing test patterns to be reused across different designs and configurations, maintaining adaptability while achieving high-speed parallel testing.
Solution Approach 2:
The patent implements dynamic resource allocation and configuration that allows test patterns to be flexibly adapted to different designs. The system can dynamically adjust how patterns are distributed and executed across parallel APGs, enabling reuse of old patterns in new designs without sacrificing testing speed.
3Productivity
If test code is designed for parallel APG usage, then testing throughput is improved, but the time required to develop new test patterns increases
Solution Approach 1:
The patent implements a universal programming interface that allows test patterns to be written once and executed by multiple parallel APGs. This eliminates the need to create separate test code for each APG, significantly reducing test development time while maintaining high throughput parallel testing capabilities.
Solution Approach 2:
The patent enables test patterns to be copied and reused across multiple parallel APG instances. Instead of manually creating unique test code for each generator, the same pattern can be replicated and adapted to different APGs, reducing development time while achieving parallel testing throughput.
Data Source
AI summary
An integrated circuit tester is described that utilizes methods of programming parallel coupled Algorithmic Pattern Generators (APGs) to generate test vector sequences and part commands with sub-instruction repeats. This enables simpler test programming and ease of test conversion to new part speed grades, steppings, or part designs. In one embodiment, a sub-instruction repeat is utilized to enable adjustment of the timing of test vector sequences and part commands sent to an integrated circuit device under test (DUT) so that the test can be adjusted for new part speed grades and/or steppings. In another embodiment, a sub-instruction repeats are utilized to enable adjustment of the timing of a memory device inputs, memory commands and test vector sequences so that the test can be adjusted for new memory device speed grades.