Application Memory Backing Store for Processor State
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Solution Overview
Problem
The existing methods for supporting processor extensions in operating systems are cumbersome and performance-intensive, particularly in multiprocessor systems, as they require significant OS involvement and storage, leading to inefficiencies in context switching and resource management.
Innovation Solution
The use of application memory as a backing store for processor state information allows for OS-agnostic and transparent management of processor extensions, enabling state save and restore operations without OS involvement, thus minimizing performance overhead and supporting new processor features without additional OS storage requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the OS provides storage in PCB or other OS structures for processor extensions, then the extensions can be supported, but the device complexity and storage requirements increase
Solution Approach 1:
The patent extracts the processor extension state storage from the OS-controlled PCB structures and relocates it to application-level data structures in user space. This allows processor extensions to be supported without increasing OS structure complexity, as the extension state is now managed separately from core OS data structures.
Solution Approach 2:
The patent introduces an intermediary mechanism (the application-level backing store with hardware-managed state) that mediates between the processor extensions and the OS. This intermediary allows extensions to be supported without requiring direct OS involvement or increases to OS data structures.
2Reliability
If the OS performs full state save upon context switch, then state coherency is maintained, but the productivity and performance deteriorate
Solution Approach 1:
The patent applies partial action by saving only the necessary processor extension state to the application-level backing store during context switches, rather than performing full state saves. The hardware automatically manages the state persistence, allowing coherency to be maintained with minimal intervention and reduced performance overhead.
Solution Approach 2:
The patent enables self-service by allowing the processor hardware to automatically manage the extension state in the application-level backing store without OS involvement. The hardware handles state persistence and restoration transparently, maintaining coherency while eliminating the performance penalty of OS-managed full state saves.
3Loss of time
If lazy save and restore mechanisms are implemented, then the loss of time is reduced, but the reliability and state coherency may be compromised in multiprocessor systems
Solution Approach 1:
The patent extracts the state management responsibility from the OS and places it in the hardware, which automatically manages the application-level backing store. This extraction allows lazy save mechanisms to work reliably in multiprocessor systems because the hardware ensures state coherency without OS coordination overhead.
Solution Approach 2:
The hardware-managed application-level backing store acts as an intermediary that ensures state coherency across multiple processors. This intermediary mechanism allows lazy save and restore to work reliably in SMP systems by providing a centralized, hardware-enforced state storage that all processors can access consistently.
4Adaptability or versatility
If new processor features are added, then the adaptability improves, but additional storage space in PCB or OS data structures is required
Solution Approach 1:
The patent extracts the storage requirement for processor extension state from the OS data structures and places it in application-level memory. This allows new processor features to be added without requiring additional OS storage space, as each application allocates its own backing store independently of the OS.
Solution Approach 2:
The application-level backing store serves multiple functions: it stores processor extension state, supports new processor features, and eliminates the need for OS storage allocation. This universal storage mechanism handles all processor extension state requirements without consuming additional OS data structure space.
Data Source
AI summary
In one embodiment, the present invention includes a method for requesting an allocation of memory to be a backing store for architectural state information of a processor and storing the architectural state information in the backing store using an application. In this manner, the backing store and processor enhancements using information in the backing store may be transparent to an operating system. Other embodiments are described and claimed.