Application Processor PLL Sleep Control for Low-Power Display Timing
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Solution Overview
Problem
Existing application processors face challenges in managing power consumption efficiently during low-frequency display operations, particularly in video modes that require dynamic refresh rates, leading to increased power consumption due to continuous operation of the phase-locked loop (PLL) even during idle periods.
Innovation Solution
The application processor incorporates a phase locked loop circuit (PLL) with sleep control logic, an always-on video timer, and clock switching logic to enter and exit sleep modes dynamically, using an always-on clock during idle periods to minimize power consumption while maintaining video timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the PLL operates continuously to maintain video timing, then display timing accuracy is improved, but power consumption increases
Solution Approach 1:
The system performs preliminary actions by maintaining the PLL in a ready state with minimal operation during idle periods, allowing it to quickly resume full operation when frame updates are needed. The video timer circuit generates advance wake-up signals before the actual frame update deadline, ensuring the PLL is prepared in time without requiring continuous full-power operation.
Solution Approach 2:
The system implements periodic action by putting the PLL into sleep mode during idle periods between frame updates and waking it up only when needed. The video timer circuit controls periodic wake-up signals based on frame timing requirements, creating a rhythm of sleep and active states that reduces average power consumption while maintaining display timing accuracy.
2Use of energy by moving object
If the PLL enters sleep mode to reduce power consumption, then power efficiency is improved, but frame update responsiveness deteriorates
Solution Approach 1:
The video timer circuit performs preliminary actions by generating wake-up signals in advance of when the PLL needs to be fully operational. This advance notification allows the PLL to wake up from sleep mode with sufficient time to lock and prepare for the upcoming frame update, ensuring responsiveness is not compromised while still benefiting from power savings during idle periods.
3Speed
If the PLL operates at full power to ensure immediate frame updates, then responsiveness is improved, but power consumption increases
Solution Approach 1:
The system applies periodic action by alternating between sleep mode and active operation based on frame timing requirements. The video timer circuit creates a periodic pattern where the PLL sleeps during idle periods and wakes up only when frame updates are needed, achieving both power efficiency and responsiveness by matching operational states to actual display requirements.
Solution Approach 2:
The system implements dynamics by making the PLL operational state flexible and adaptive rather than fixed. The PLL dynamically transitions between sleep and active states based on real-time display needs, controlled by the video timer circuit. This dynamic behavior allows the system to optimize power consumption while maintaining responsiveness when required.
Data Source
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AI summary
An application processor is provided. The application processor includes: a phase locked loop circuit (PLL); a sleep control logic circuit configured to control the PLL to enter and exit a sleep mode; a wake-up generation logic circuit configured to provide a wake-up request signal to the sleep control logic circuit to control the PLL to exit the sleep mode based on an early wake-up signal; an always-on video timer circuit configured to output a synchronization signal to a display driving chip in a sleep mode section and generate the early wake-up signal; a display video timer circuit configured to receive the synchronization signal from the always-on video timer and indicate the sleep control logic to provide an idle section; and clock switching logic circuit configured to alternately provide, as an operation clock of the sleep control logic, one of an always-on clock and a word clock.