Approximate Cache Memory With Quality-Aware Controller
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Solution Overview
Problem
Current cache memory technologies, particularly spintronic-based ones, face challenges in reducing energy usage due to high energy requirements for read and write operations, and existing approximate computing methods primarily focus on processing rather than storage, leaving a need for innovative architectures to optimize energy efficiency in cache memories.
Innovation Solution
The introduction of a quality-aware cache controller (QACC) that manages approximation techniques such as partial reads/writes, lower read currents, skipped writes, reduced write duration, and skipped refreshes to minimize energy consumption while maintaining acceptable quality in cache operations, specifically designed for both CMOS and spintronic cache structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional cache memory operations (read/write/refresh) are performed with full precision, then data accuracy is maintained, but energy consumption increases
Solution Approach 1:
The patent applies partial action by performing approximate computing operations in the cache memory. Instead of executing full precision read/write/refresh operations on all cache data, the system selectively applies approximation techniques to less critical data or operations, thereby reducing energy consumption while maintaining acceptable accuracy for applications that can tolerate approximate results.
Solution Approach 2:
The patent changes the precision parameter of cache operations dynamically. By adjusting the level of approximation based on data importance, access patterns, and application requirements, the system can switch between full precision and approximate modes, optimizing the trade-off between energy consumption and data accuracy.
2Use of energy by moving object
If approximate computing methods are applied in cache storage, then energy consumption is reduced, but data precision deteriorates
Solution Approach 1:
The patent applies local quality by differentiating the treatment of different cache data based on their importance and precision requirements. Critical data that requires high precision is handled with full accuracy operations, while non-critical data undergoes approximate operations. This localized application of approximation techniques reduces overall energy consumption while maintaining data precision where necessary.
Solution Approach 2:
The system performs partial approximation actions selectively on specific cache entries rather than applying uniform approximation to all data. By identifying which cache lines or data elements can tolerate approximation, the system applies partial action only where appropriate, thereby reducing energy consumption without significantly compromising overall data precision.
3Quantity of substance
If spintronic-based cache memory is used, then storage capacity increases, but energy usage for read/write operations increases
Solution Approach 1:
The patent applies partial action by selectively performing approximation operations on spintronic cache data based on access patterns and data importance. Instead of executing full precision operations on all spintronic cache entries, the system identifies candidates for approximation and applies reduced-precision operations only to those, thereby reducing the energy usage for read/write operations while maintaining storage capacity.
Solution Approach 2:
The patent changes the operational parameters of spintronic cache memory by dynamically adjusting the precision level of read/write operations. By switching between full precision and approximate modes based on workload characteristics, the system optimizes energy usage for read/write operations while preserving the high storage capacity benefits of spintronic technology.
Data Source
AI summary
An approximate cache system is disclosed. The system includes a quality aware cache controller (QACC), a cache, a quality table configured to receive addresses and a quality specification from the processor associated with each address and further configured to provide the quality specification for each address to the QACC, wherein the QACC controls approximation is based on one or more of i) approximation through partial read operations; ii) approximation through lower read currents; iii) approximation through skipped write operations; iv) approximation through partial write operations; v) approximations through lower write duration; vi) approximation through lower write currents; and vii) approximations through skipped refreshes.