Approximate DPD Actuator Using Shift-Based Multiplication for 5G Radios
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Solution Overview
Problem
Conventional Digital Predistortion (DPD) systems consume significant power due to the use of conventional multipliers in the forward path, making it difficult to integrate them with power amplifiers in radio devices without excessive heating, and they require complex cooling systems.
Innovation Solution
The proposed DPD system replaces conventional multipliers with an approximate multiplication function using bit shifting operations, where each LUT entry is represented by summation or subtraction of multiple powers of 2, allowing for energy-efficient shift and accumulate operations, reducing power consumption by 72% and area usage by 86% while maintaining the required Adjacent Channel Leakage Ratio (ACLR) within 5G specifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional multipliers are used in the DPD forward path, then multiplication accuracy is maintained, but power consumption increases significantly
Solution Approach 1:
The patent replaces expensive conventional multipliers with a cheaper approximate multiplication function that uses bit-shifting and addition operations. This approximation accepts some loss in multiplication accuracy but achieves significant power consumption reduction, making the DPD system viable for integration with power amplifiers in radio devices
Solution Approach 2:
The patent changes the computational parameters by representing LUT entries as summation or subtraction of multiple powers of 2. This parameter transformation enables the use of bit-shifting operations instead of conventional multiplication, fundamentally changing how the calculation is performed to reduce power consumption while maintaining acceptable accuracy
2Measurement precision
If conventional multipliers are used in the DPD forward path, then calculation precision is maintained, but area usage increases
Solution Approach 1:
The patent segments the multiplication operation into multiple simpler steps: bit-shifting operations and addition operations. By breaking down the conventional multiplier into these discrete segments, the implementation area is significantly reduced while maintaining acceptable calculation precision for the DPD application
Solution Approach 2:
The patent substitutes the mechanical conventional multiplier circuit with a different computational mechanism using bit-shifting and addition. This substitution replaces a complex multiplier architecture with simpler operations that require less circuit area while achieving the same functional goal of signal predistortion
3Area of stationary object
If DPD system is integrated with radio on the same chip, then area efficiency is improved, but power consumption and heating increase
Solution Approach 1:
The patent employs approximate multiplication that sacrifices some precision for dramatically reduced power consumption and area usage. This approximation enables the DPD system to be integrated on the same chip as the radio and power amplifier without generating excessive heat or consuming prohibitive power
Solution Approach 2:
By changing the computational parameters to use powers of 2 representation and bit-shifting operations, the patent reduces the power consumption and area requirements of the DPD system, making chip-level integration feasible without excessive heating or power budget exhaustion
Data Source
AI summary
Systems and methods are disclosed herein for providing efficient Digital Predistortion (DPD). In some embodiments, a system comprises a DPD system comprising a DPD actuator. The DPD actuator comprises a Look-Up Table (LUT), selection circuitry, and an approximate multiplication function. Each LUT entry comprises information that represents a first set of values {p1, p2, . . . , pk} and a second set of values {s1, s2, . . . , sk} that represent a LUT value of s1·2p<sub2>1</sub2>+s2·2p<sub2>2</sub2>+ . . . +sk·2p<sub2>k </sub2>where each value si ∈{+1 , −1} where k≥2. The selection circuitry is operable to, for each input sample of an input signal, select a LUT entry based on a value derived from the input sample that is indicative of a power of the input signal. The approximate multiplication function comprises shifting and combining circuitry that operates to, for each input sample, shift and combine bits that form a binary representation of the input sample in accordance with {p1, p2, . . . , pk} and {s1, s2, . . . , sk} to provide an output sample.