Approximate DPD Actuator Using Shift-Add LUT Multiplication
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Solution Overview
Problem
Digital Predistortion (DPD) systems in radio devices face high power consumption due to conventional multipliers in the forward path, which prevents integration with power amplifiers on the same chip, especially in 5G radios with multiple power amplifiers.
Innovation Solution
The proposed solution replaces conventional multipliers with an approximate multiplication function using bit shifting and accumulation operations, representing Look-Up Table (LUT) entries as combinations of powers of 2, reducing power consumption and area requirements while maintaining Adjacent Channel Leakage Ratio (ACLR) within 5G specifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional multipliers are used in the forward path of DPD system, then multiplication accuracy is maintained, but power consumption and area increase significantly
Solution Approach 1:
The patent applies partial action by using approximation instead of exact multiplication. The LUT stores pre-computed values that approximate the multiplication result, and the bit-shifting operation provides a simplified multiplication that is sufficiently accurate for DPD applications. This partial accuracy approach achieves 72% dynamic energy reduction while maintaining acceptable ACLR performance within 5G specifications.
Solution Approach 2:
The patent replaces expensive conventional multipliers with cheaper bit-shifting and accumulation operations. The LUT entries are stored in a compact format using only k bits per entry instead of requiring full-precision multiplier circuits. This substitution dramatically reduces both area and power consumption while providing sufficient accuracy for the DPD function.
2Area of stationary object
If conventional multipliers are used in the forward path of DPD system, then computation precision is maintained, but device area increases
Solution Approach 1:
The patent segments the multiplication operation into discrete bit-shifting steps. Instead of using a single complex multiplier circuit, the computation is divided into k bit-shifting operations followed by accumulation. The LUT is also segmented into k-bit entries representing power-of-2 combinations. This segmentation reduces the area requirement from a large multiplier circuit to smaller, distributed shift and add circuits.
Solution Approach 2:
The patent uses partial precision representation by storing LUT entries in k bits instead of full precision. The bit-shifting operation processes only the necessary number of bits to achieve sufficient accuracy. This partial precision approach maintains computation precision within acceptable bounds while dramatically reducing the area required for LUT storage and processing.
3Adaptability or versatility
If DPD system is integrated with radio on the same chip, then system integration is improved, but power consumption and area constraints are violated
Solution Approach 1:
The patent changes the operational parameters of the DPD system by using bit-shifting instead of conventional multiplication. This parameter change in the computational method reduces the power consumption and area requirements, enabling integration with the radio on the same chip. The k-bit LUT representation and bit-shifting operation create a low-power implementation suitable for integrated circuits.
4Adaptability or versatility
If DPD system is integrated with radio on the same chip, then system integration is improved, but device area increases
Solution Approach 1:
The patent changes the structural parameters by representing LUT entries using only k bits per entry instead of full-precision values. This parameter change in the data representation format dramatically reduces the area required for LUT storage. The bit-shifting operation also requires less area than conventional multipliers, enabling chip integration within area constraints.
Data Source
AI summary
Systems and methods are disclosed herein for providing efficient Digital Predistortion (DPD). In some embodiments, a system comprises a DPD system comprising a DPD actuator. The DPD actuator comprises a Look-Up Table (LUT), selection circuitry, and an approximate multiplication function. Each LUT entry comprises information that represents a first set of values {p1, p2, . . . , pk} and a second set of values {s1, s2, . . . , sk} that represent a LUT value of s1·2p<sub2>1</sub2>+s2·2p<sub2>2</sub2>+ . . . +sk·2p<sub2>k </sub2>where each value si∈{+1,−1} where k≥2. The selection circuitry is operable to, for each input sample of an input signal, select a LUT entry based on a value derived from the input sample that is indicative of a power of the input signal. The approximate multiplication function comprises shifting and combining circuitry that operates to, for each input sample, shift and combine bits that form a binary representation of the input sample in accordance with {p1, p2, . . . , pk} and {s1, s2, . . . , sk} to provide an output sample.