Approximate Memory Architecture for DRAM Refresh Power Reduction
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Solution Overview
Problem
Deep learning applications face significant power consumption due to periodic refresh operations in DRAM devices, which can account for up to 50% of total power consumption, especially as DRAM density increases, and existing methods for reducing refresh power are either costly or result in accuracy degradation.
Innovation Solution
An approximate memory architecture that stores data in a transposed manner, where more significant bits are refreshed at a normal rate and less significant bits are refreshed at a slower rate, allowing for a reduction in the number of refresh operations and power consumption while tolerating some data errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If periodic refresh operations are performed on all DRAM cells to preserve data integrity, then data correctness is maintained, but power consumption increases significantly
Solution Approach 1:
The patent applies local quality by differentiating refresh operations based on data location and significance. MSBs stored in first through ninth rows receive normal refresh operations to maintain high reliability, while LSBs in tenth through thirty-second rows undergo approximate refresh operations with extended periods, accepting lower reliability in exchange for reduced power consumption. This localized differentiation resolves the contradiction by applying appropriate refresh intensity only where needed.
Solution Approach 2:
The patent segments the DRAM memory into multiple rows (first through thirty-second rows) and further segments data into MSBs and LSBs. By organizing memory rows to store specific bit significance levels and applying different refresh strategies to different row groups, the patent enables selective refresh that maintains data correctness for critical bits while reducing refresh operations for less critical bits, thereby reducing overall power consumption.
2Quantity of substance
If DRAM density is increased to improve storage capacity, then memory capacity increases, but refresh power consumption increases proportionally
Solution Approach 1:
The patent applies local quality by differentiating refresh operations based on data location and significance. MSBs stored in first through ninth rows receive normal refresh operations to maintain high reliability, while LSBs in tenth through thirty-second rows undergo approximate refresh operations with extended periods, accepting lower reliability in exchange for reduced power consumption. This localized differentiation resolves the contradiction by applying appropriate refresh intensity only where needed.
3Use of energy by moving object
If refresh rate is reduced to save power consumption, then power consumption decreases, but data loss occurs in DRAM cells
Solution Approach 1:
The patent applies local quality by differentiating refresh operations based on data location and significance. MSBs stored in first through ninth rows receive normal refresh operations to maintain high reliability, while LSBs in tenth through thirty-second rows undergo approximate refresh operations with extended periods, accepting lower reliability in exchange for reduced power consumption. This localized differentiation resolves the contradiction by applying appropriate refresh intensity only where needed.
Solution Approach 2:
The patent applies the principle of disposable objects by treating LSBs as less critical data that can tolerate loss. The approximate refresh operation intentionally allows LSBs to be lost or corrupted, similar to using a cheaper, shorter-lived resource. Since LSBs contribute less to overall data accuracy, their potential loss is acceptable, enabling reduced refresh operations and lower power consumption while maintaining acceptable data integrity for critical MSBs.
4Ease of operation
If data is stored in conventional manner, then memory access is straightforward, but all data requires same refresh rate increasing power consumption
Solution Approach 1:
The patent segments the DRAM memory into multiple rows (first through thirty-second rows) and further segments data into MSBs and LSBs. By organizing memory rows to store specific bit significance levels and applying different refresh strategies to different row groups, the patent enables selective refresh that maintains data correctness for critical bits while reducing refresh operations for less critical bits, thereby reducing overall power consumption.
Solution Approach 2:
The patent applies local quality by differentiating refresh operations based on data location and significance. MSBs stored in first through ninth rows receive normal refresh operations to maintain high reliability, while LSBs in tenth through thirty-second rows undergo approximate refresh operations with extended periods, accepting lower reliability in exchange for reduced power consumption. This localized differentiation resolves the contradiction by applying appropriate refresh intensity only where needed.
Data Source
AI summary
The provided is a method of controlling a dynamic random-access memory (DRAM) device comprising: storing a plurality of pieces of data consisting of a plurality of bits in a memory in a transposed manner; setting at least one refresh period for each of a plurality of rows constituting the memory; and performing a refresh operation of the memory on the basis of the set refresh period.