Approximated LLL Algorithm Seed Expansion for Cryptography
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Solution Overview
Problem
Lattice basis reduction methods, such as the LLL algorithm, are computationally demanding and may not converge correctly on processors with limited resources, making them unsuitable for generating cryptographic keys efficiently.
Innovation Solution
An approximated version of the LLL algorithm is used, which omits vector swapping and simplifies calculations, and a trial seed is evaluated offline to ensure successful expansion, with a more powerful computer selecting a seed that guarantees the approximated expansion process meets required criteria, storing the seed in non-volatile memory for use by the target processor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the full LLL algorithm is used for lattice basis reduction, then the output basis is guaranteed to be reduced and nearly orthogonal, but the computational complexity and resource requirements become too high for processors with limited resources
Solution Approach 1:
The patent extracts and removes the vector swapping step from the full LLL algorithm, creating a simplified version that retains the essential lattice basis reduction functionality while significantly reducing computational complexity. This extraction allows the algorithm to run on processors with limited resources while still producing useful reduced bases for cryptographic key generation.
Solution Approach 2:
The patent applies partial action by implementing an incomplete version of the LLL algorithm that performs only some of the reduction steps (omitting vector swapping). This partial implementation is sufficient for the cryptographic application's needs and balances computational feasibility with output quality, allowing deployment on resource-constrained devices.
2Device complexity
If the LLL algorithm is simplified by omitting vector swapping, then the computational resources required are reduced, but the output basis may not satisfy the required reduction criteria
Solution Approach 1:
The patent applies preliminary action by pre-selecting and storing seed values that are guaranteed to work correctly with the simplified LLL algorithm. These seeds are chosen in advance through testing to ensure they produce valid cryptographic keys when processed by the approximated algorithm, thereby compensating for the algorithm's reduced precision guarantees.
Solution Approach 2:
The patent changes the approach from modifying the algorithm's parameters to modifying the input seed parameters. By carefully selecting specific seed values that are compatible with the simplified algorithm's behavior, the system achieves reliable cryptographic key generation without requiring the full LLL algorithm's precision guarantees.
3Reliability
If a powerful computer is used to select and test seed values offline, then the probability of finding suitable seeds increases, but the initial setup time and computational effort increase
Solution Approach 1:
The patent performs seed selection and validation in advance using powerful computers, storing only the validated seeds in the final device. This preliminary action transfers the computational burden from the resource-constrained target processor to an offline setup phase, ensuring that the stored seeds are guaranteed to work with the simplified algorithm while minimizing the time and resources needed during actual key generation.
Data Source
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AI summary
A method for computation is described, the method including configuring a processor to expand input seed values into respective output data values using an approximated expansion process such that the output data values are not guaranteed to satisfy a required output data criterion, selecting a seed value so that an output data value generated by the processor by application of the approximated expansion process to the selected seed value will yield an output data value that satisfies the required output data criterion, and storing the selected seed value in a non-volatile memory to be accessed by the processor. Related apparatus and systems are also described.