Approximation Circuitry for Low-Power Bitwise Operations
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Solution Overview
Problem
Conventional digital circuitry for mobile and wearable devices consumes excessive power for operations like multiplication and division, making it unsuitable for devices with limited power availability, such as those in IoT and 5G communications networks.
Innovation Solution
The implementation of approximation circuitry that uses bitwise operations to generate approximate results, reducing power consumption by storing operands in intermediate registers and employing a significant digit detector to identify and store only the most significant bits, thereby reducing the number of bits processed, and utilizing a lookup table to generate approximate results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional circuitry is used to perform multiplication and division operations, then the operations can be performed with full precision, but the power consumption is excessive for mobile and wearable devices
Solution Approach 1:
The patent extracts and processes only the most significant bits of the operands using a significant digit detector, rather than processing all bits. This extraction approach reduces the number of bits that need to be processed in subsequent multiplication or division operations, thereby reducing power consumption while maintaining acceptable precision for the most significant portions of the result
Solution Approach 2:
The patent applies partial action by performing operations on only a subset of the bits (the most significant bits) rather than all bits. The significant digit detector identifies and processes only the necessary most significant bits, leaving less significant bits unprocessed. This partial processing achieves acceptable results for many applications while significantly reducing the computational effort and power consumption
2Use of energy by moving object
If bitwise operations are used to reduce power consumption, then power consumption is reduced, but the result is only approximate rather than precise
Solution Approach 1:
The patent applies local quality by ensuring high precision for the most significant bits of the result while accepting lower precision for less significant bits. The significant digit detector focuses computational resources on identifying and processing the most significant bits, which have the greatest impact on the overall result value. This localized precision approach provides acceptable accuracy for the most important portions of the calculation while reducing overall computational requirements
Solution Approach 2:
The patent performs partial processing on only the most significant bits rather than all bits. By applying bitwise operations selectively to the most significant bits identified by the significant digit detector, the circuit achieves acceptable approximate results with significantly reduced power consumption compared to full-precision operations
3Speed
If a Lookup Table is used to store pre-computed values, then operation speed can be improved, but the LUT expands exponentially with increasing size of the numbers
Solution Approach 1:
The patent segments the operand processing by dividing the N-bit operands into multiple smaller groups of bits. The significant digit detector processes these segmented bit groups to identify the most significant bits. This segmentation allows the use of smaller, more manageable lookup tables for each segment rather than requiring a single large LUT that would expand exponentially with the full operand size
Solution Approach 2:
The patent applies partial action by using lookup tables only for the most significant bits rather than all bits of the operands. The significant digit detector identifies which bits are most significant, and lookup tables are applied selectively to those bits. This partial application of LUTs provides speed improvement for the most critical portions of the calculation while avoiding the exponential growth problem of using LUTs for all bits
Data Source
AI summary
Approximation circuitry utilizes bitwise operations on operands to provide approximate results of operations on the operands. A significant digit detector utilizes bitwise operations on the received operands to identify or detect approximate most significant bits in the operands, and then utilizes these identified most significant bits to generate approximate values for each of the operands. Intermediate registers receive and store the approximate values from the significant digit detector. A combinatorial network, such as a lookup table (LUT), thereafter utilizes the approximate values stored in the intermediate registers to generate an approximate result. The approximate result has a value that is an approximate value of a given operation, such as multiplication or division, on the operands provided to the significant digit detector.