APSS Peak Current Mitigation via Boot-Time Characterization

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Solution Overview

Problem

Existing peak current mitigation solutions in SoCs often fail to ensure that the power budget is not exceeded, while also detrimental to performance, especially when multiple processor clusters share the same supply voltage rail.

Innovation Solution

The proposed solution involves obtaining voltage and leakage current values at boot time to estimate peak current ranges, using a preconfigured map to determine throttling levels, and applying these throttling levels dynamically at runtime to mitigate peak current without unnecessary performance impact.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional peak current mitigation solutions are applied, then power budget constraints are enforced, but performance is detrimentally impacted

Engineering Contradiction:
Improvepower budget constraint enforcementVSAvoidprocessor performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system performs preliminary characterization during manufacturing to determine each SoC's actual peak current, storing this information for runtime use. This preliminary action allows the runtime system to make informed decisions about throttling based on actual device characteristics rather than applying uniform mitigation, thus preventing unnecessary performance degradation while ensuring power budget compliance.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system changes the parameter of throttling level from a fixed uniform value to a dynamic value based on actual peak current measurements. By mapping measured peak current values to specific throttling levels, the system adjusts processor operating parameters adaptively, ensuring power budget enforcement without excessive performance impact on devices with lower actual current draw.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If uniform throttling is applied to all SoCs, then power budget is ensured, but unnecessary performance degradation occurs on SoCs with lower peak current

Engineering Contradiction:
Improvepower budget complianceVSAvoidprocessor throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system applies local quality by customizing the throttling level for each individual SoC based on its specific peak current characteristics. Instead of a blanket uniform throttling approach, each device receives a tailored throttling level that matches its actual power consumption profile, ensuring that devices with lower peak current experience minimal or no throttling while still maintaining power budget compliance.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system uses feedback from manufacturing measurements of actual peak current to dynamically adjust throttling levels. The measured peak current values feed into a mapping mechanism that determines the appropriate throttling level, creating a closed-loop system that adapts to each device's actual behavior rather than relying on worst-case estimates, thereby avoiding unnecessary performance degradation.

Inventive Principle:
Principle #23Feedback

3Ease of manufacture

If aggressive power grid sizing optimization is used, then SoC cost is reduced, but meeting power budget becomes challenging when all cores operate at maximum frequency

Engineering Contradiction:
ImproveSoC manufacturing costVSAvoidpower budget adherence
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The system performs preliminary measurement and characterization of each SoC's actual peak current during manufacturing, capturing the specific power consumption characteristics of each device. This preliminary action enables the use of more aggressive (cheaper) power grid designs while still ensuring power budget compliance, because the runtime system can accurately determine the appropriate throttling level based on actual measurements rather than worst-case assumptions.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system enables each SoC to self-determine its appropriate throttling level based on its own measured characteristics. By using the measured peak current to select the throttling level, the system allows each device to serve itself in managing its power consumption, eliminating the need for overly conservative uniform throttling and enabling more aggressive cost-optimized power grid designs.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12332711B2Systems and methods for mitigating peak current and improving overall performance
Publication Date: 2025.06.17 QUALCOMM INC
  • US12332711B2 patent drawing
  • US12332711B2 patent drawing
  • US12332711B2 patent drawing

AI summary

A system for performing peak current mitigation in an application programming subsystem (APSS) dynamically performs mitigation based at least in part on power rail voltage and leakage current obtained at boot time. The voltage and leakage current obtained at boot time are used to estimate peak current. A map that is generated prior to boot time maps estimated peak current to throttling level and dictates different levels of throttling to be performed for different ranges of estimated peak current. At boot time, the map is used to map the estimated peak current to a level of throttling to be applied. If conditions at run time indicate that peak current is occurring or is likely to occur soon, the mapped level of throttling is applied to mitigate the peak current.