Auxiliary Processing Unit Memory Configuration via Communication Link
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Solution Overview
Problem
Multiprocessor systems face inefficiencies and costs in providing communication links for all processing units, and upgrading these systems can result in data loss or alteration, making reconfiguration and upgradation complex and requiring sophisticated programming techniques.
Innovation Solution
A method for configuring an Auxiliary Processing Unit (APU) in a multiprocessor system involves dividing memory into application, boot, and common sectors, disabling interrupts, mapping communication link interrupts, receiving configuration code selectively into these sectors, and updating the common sector, allowing for efficient reconfiguration and upgradation without external programming interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a communication link is provided for each processing unit to interact with external resources, then the processing unit can communicate with external resources, but extra real estate on silicon is required which increases area and cost
Solution Approach 1:
The communication link is designed to serve multiple functions: it is used both for configuration of the processing unit and for runtime communication with external resources. This multi-functionality eliminates the need for separate dedicated communication interfaces, reducing silicon area while maintaining full communication capability.
2Adaptability or versatility
If on board memory is updated during system upgradation, then the system can be upgraded with new functionalities, but data loss and/or alteration occurs
Solution Approach 1:
Before updating the on-board memory, the system performs preliminary actions including disabling interrupts, protecting critical data structures, and preparing backup copies of essential data. This ensures that the upgrade process does not result in data loss or alteration, maintaining reliability while enabling system upgradability.
3Adaptability or versatility
If sophisticated programming techniques like JTAG, spy Bi-ware, or UART based programming are used for reconfiguration, then the processing unit can be reconfigured, but the process becomes complex and requires service personnel
Solution Approach 1:
The processing unit is equipped with self-service reconfiguration capabilities through integrated configuration modes that can be activated without external programming equipment. The unit can autonomously load configuration data from external sources via its communication link, eliminating the need for complex JTAG, spy Bi-ware, or UART programming techniques and removing the requirement for specialized service personnel.
4Productivity
If interrupts are enabled during memory updating, then normal operation can continue, but data loss or alteration may occur
Solution Approach 1:
The interrupt handling system is segmented into critical and non-critical interrupts. During memory updating, only non-critical interrupts are disabled while critical interrupts remain enabled to maintain operational continuity. This selective interrupt management ensures data integrity for update-related operations while allowing essential system functions to continue operating.
Data Source
AI summary
A method for configuration of an Auxiliary Processing Unit (APU) of multiprocessor system is presented. The multiprocessor system has at least a Main Processing Unit (MPU) coupled to the APU via a communication link. The APU has at least a first memory and a second memory. The method includes a plurality of steps. At step the first memory is divided into an application sector, a boot sector and a common sector. At another step interrupts of the APU except interrupt/s that is/are being received via the communication link are disabled. At a further step interrupt vector/s pertaining to the communication link is/are mapped to the boot sector of the first memory. At another step a configuration code is received selectively into the application sector of the first memory and into the second memory. At a further step the interrupt/s that is/are being received via the communication link are disabled. At a further step the common sector of the first memory is updated from the second memory.