Arbitration Controller Virtual Channels Time-out Counters

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Solution Overview

Problem

Current semiconductor integrated apparatuses face challenges in efficiently arbitrating requests to shared resources like memory, particularly in managing latency and priority, which affects power efficiency and leads to Head of Line (HOL) blocking.

Innovation Solution

A data processing apparatus with a controller that sets Time-out Counters (TCs) for requests based on priority levels, allocates virtual channels corresponding to priority levels, and selects requests for transmission to the slave device based on TC expiration, preventing HOL blocking and ensuring efficient processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If traditional arbitration methods are used to manage requests to shared memory, then the system structure remains simple, but power efficiency deteriorates and latency increases due to Head of Line blocking

Engineering Contradiction:
Improvepower efficiencyVSAvoidarbitration structure complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent segments the arbitration structure into multiple arbitration units, each handling specific request groups. Virtual channels are divided into multiple queues (head queue, middle queue, tail queue) to prevent HOL blocking. This segmentation allows parallel processing of different request types while maintaining power efficiency through selective activation of arbitration units based on request priority and type.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces virtual channels as an additional dimension for request management, organizing requests into multiple queues within each virtual channel. This dimensional organization separates requests by priority and type, allowing the system to process high-priority requests independently without being blocked by low-priority requests in traditional FIFO structures.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Loss of time

If priority-based arbitration is implemented, then latency for high-priority requests is reduced, but the arbitration mechanism becomes more complex

Engineering Contradiction:
Improverequest latencyVSAvoidarbitration mechanism complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by pre-organizing requests into different virtual channels and queues based on their priority and type before arbitration. Requests are classified and placed in appropriate queues (head, middle, tail) in advance, so that when arbitration occurs, the system can quickly select from pre-organized groups rather than sorting through all requests, reducing latency while keeping the arbitration logic relatively simple.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Different arbitration strategies are applied to different request groups locally. High-priority requests in head queues receive preferential treatment with dedicated arbitration units, while lower-priority requests in tail queues use different arbitration logic. This local differentiation optimizes latency for critical requests without unnecessarily complicating the arbitration of less critical requests.

Inventive Principle:
Principle #3Local quality

3Productivity

If virtual channels are allocated to request groups, then HOL blocking is prevented, but the system complexity increases

Engineering Contradiction:
Improverequest processing efficiencyVSAvoidvirtual channel management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent makes the arbitration units universal by designing them to handle multiple types of requests across different virtual channels. Each arbitration unit can service requests from any virtual channel, and the same basic arbitration logic is reused across different request types. This multi-functionality reduces the need for separate dedicated arbitration logic for each virtual channel, managing complexity while maintaining high productivity through parallel request processing.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11372794B2Data processing apparatus for arbitration of requests and operation method thereof
Publication Date: 2022.06.28 SK HYNIX INC
  • US11372794B2 patent drawing
  • US11372794B2 patent drawing
  • US11372794B2 patent drawing

AI summary

A data processing apparatus may include a master device, a slave device, and a controller configured to arbitrate communication between the master device and the slave device by: setting a respective Time-out Counter (TC) for each of requests transmitted from the master device, allocating one or more virtual channels to each of one or more request groups, the one or more virtual channels respectively corresponding to priority levels, associating a request with a virtual channel corresponding to the priority level of the request, for each request group, selecting one of the leading requests of the respective virtual channels according to the TCs and transmitting the selected request to the slave device.