2D Arbiter Array Address Decoding to Reduce Interconnect Wires
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Solution Overview
Problem
The sheer volume of conductive pathways on large integrated circuits (ICs) becomes problematic due to the non-linear increase with the number of requesting units and resources, leading to space issues for the circuitry.
Innovation Solution
A two-dimensional array of requesting and granting agents with row and column address decoders that reduce the number of wires needed by decoding addresses at the row and column levels, rather than within each granting agent, allowing for efficient address determination and resource access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional crossbar connections are used to connect requesting units to resources, then each requesting unit can access each resource directly, but the number of conductive pathways increases non-linearly, leading to excessive space requirements
Solution Approach 1:
The patent segments the addressing function by introducing row address decoders and column address decoders that separately decode different portions of the address. This segmentation allows the system to use fewer conductive pathways while maintaining full access capability, as the decoders reconstruct the full address information from partial signals.
Solution Approach 2:
The patent introduces address decoders as intermediary components between requesting units and resources. These decoders act as mediators that translate condensed address signals into specific resource selections, enabling indirect access that reduces the number of direct conductive pathways needed while preserving adaptability.
2Ease of operation
If address decoding logic is integrated within each granting agent, then address determination is straightforward, but the number of wires needed to interconnect requesting agents to granting agents increases significantly
Solution Approach 1:
The patent transitions from a one-dimensional direct connection model to a two-dimensional addressing scheme with row and column dimensions. By organizing addressing in two dimensions with separate decoders for each dimension, the system reduces wire complexity while maintaining ease of address determination through the coordinated operation of row and column decoders.
Solution Approach 2:
The patent segments the address decoding function into separate row address decoders and column address decoders, with each decoder handling a portion of the addressing task. This segmentation distributes the decoding complexity across multiple specialized components rather than concentrating it in each granting agent, reducing overall wire complexity.
Data Source
AI summary
A system comprises a plurality of requesting agents and granting agents configured in an array of rows and a plurality of columns. Corresponding to each requesting agent is a plurality of row address decoders and column address decoders, one row decoder for each row of granting agents and one column decoder for each column of granting agents. Each row decoder receives a first subset of an address' bits from a requesting agent and generates a row output bit provided to each granting agent in the row of that row address decoder. Each column decoder receives a second subset of bits of the address and generates a column output bit provided to each granting agent in the column corresponding to such column decoder. Each granting agent logically combines the row and column output bits from row and column decoders of a requesting agent to generate a request signal for the granting agent.