Multi-processor Arbiter Circuit for Scalable Parallel Control
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Solution Overview
Problem
Existing multi-processor systems face challenges in extensibility due to circuit configuration dependencies on the number of sub-processors, leading to increased development costs and complexity as the number of sub-processors grows.
Innovation Solution
A multi-processor system with an arbiter circuit that arbitrates process commands and execution results between the main processor and sub-processors, allowing for parallel control without changing the execution control circuit configuration, regardless of the number of sub-processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the main processor directly controls each sub-processor using the system bus, then the system has good observability and centralized management, but the processing load concentrates in the main processor causing congestion as the number of sub-processors increases
Solution Approach 1:
The control function is segmented from the main processor and assigned to a dedicated execution control device. This device independently manages multiple sub-processors, dividing the control workload and preventing main processor congestion while maintaining centralized management capabilities.
Solution Approach 2:
An execution control device is introduced as an intermediary between the main processor and sub-processors. This mediator handles the complex control operations, allowing the main processor to focus on high-level tasks while the intermediary manages sub-processor coordination and status monitoring.
2Productivity
If an execution control device parallelly controls sub-processors to enhance load distribution, then the processing capacity improves, but the circuit configuration must change when the number of sub-processors changes reducing extensibility
Solution Approach 1:
The execution control device is designed with a universal interface that can accommodate any number of sub-processors without requiring configuration changes. The device performs multiple functions including command distribution, status collection, and interrupt handling through a standardized architecture that scales seamlessly.
Solution Approach 2:
The system transitions from a fixed N-to-1 control architecture to a scalable many-to-one architecture by adding another dimension of control through the execution control device. This allows the system to handle variable numbers of sub-processors by simply connecting them to the universal interface without modifying the core control logic.
3Adaptability or versatility
If the circuit configuration depends on the number of sub-processors, then the system can be customized for specific applications, but the development cost and complexity increase as the number of sub-processors grows
Solution Approach 1:
The execution control device is pre-configured with a universal interface and control logic that anticipates future scaling requirements. This preliminary design decision establishes a standardized architecture that can accommodate any number of sub-processors, eliminating the need for complex custom configurations as the system grows.
Data Source
AI summary
In order to control sub-processors in parallel without losing extensibility, an execution control circuit (30), which forms a multi-processor system (1), issues a process command (CMD) to each of sub-processors (20—1 to 20—3) based on a process sequence (SEQ) designated by a main processor (10), and acquires a process status (STS) which indicates an execution result of processing executed by each of the sub-processors (20—1 to 20—3) in accordance with the process command (CMD). An arbiter circuit (40) arbitrates transfer of the process command (CMD) and the process status (STS) between the execution control circuit (30) and each of the sub-processors (20—1 to 20—3).