Arbiter Controller Limits Outstanding Read Requests
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Solution Overview
Problem
In image processing systems with multiple devices connected via high-speed serial interfaces like PCI Express, existing methods can increase read latency for some devices due to memory access by others, leading to delays in data transmission and potential formation of abnormal images during printing.
Innovation Solution
A controller with multiple communication interfaces and a second arbiter that limits the number of outstanding read requests to prevent increased read latency, ensuring that only a controlled number of requests are processed by the first arbiter, thereby managing access to memory effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple devices are connected to a communication interface and read requests are accumulated in memory, then data transfer capacity is improved, but read latency increases for some devices due to memory access by other devices
Solution Approach 1:
The patent divides the single arbitration process into two distinct arbitration stages: a first arbitration process that limits the number of outstanding read requests transmitted to memory, and a second arbitration process that manages memory access. This segmentation prevents one device from monopolizing memory access and causing latency increases for other devices, while still allowing multiple devices to transfer data efficiently.
Solution Approach 2:
The patent introduces a first arbiter as an intermediary component between the communication interface and the memory access system. This first arbiter mediates by limiting the number of outstanding read requests that can be transmitted to memory, thereby controlling the flow of requests and preventing latency increases for other devices while maintaining overall data transfer capacity.
2Speed
If the number of outstanding read requests to memory is increased, then data transmission speed is improved, but read latency for other devices increases
Solution Approach 1:
The patent implements dynamic control of outstanding read requests through the first arbiter, which adaptively limits the number of requests based on system conditions. This dynamic management allows the system to optimize data transmission speed while preventing latency increases for other devices, rather than using a fixed limit.
3Device complexity
If memory access is allowed without limitation for multiple devices, then system complexity is reduced, but read latency control becomes difficult
Solution Approach 1:
The patent segments the arbitration function into two distinct arbiters with specialized roles: the first arbiter handles limiting outstanding read requests, and the second arbiter manages memory access. This segmentation provides effective read latency control while keeping each individual arbiter relatively simple in function.
Data Source
AI summary
A controller includes a plurality of communication interfaces, a first arbiter, and a second arbiter. The first arbiter arbitrates access to a memory. The second arbiter is disposed between the plurality of communication interfaces and the first arbiter. In response to reception of a plurality of outstanding read requests to the memory from one of the plurality of communication interfaces, the second arbiter limits the number of outstanding read requests to transmit to the first arbiter.