Arbiter Verification via Counter Tracking
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Solution Overview
Problem
Dynamic simulation-based verification of arbitration schemes in hardware designs becomes intractable as the number of requestors grows, especially when requests arrive both serially and concurrently, due to the large number of cases and possible arbitration combinations, making exhaustive testing impossible.
Innovation Solution
A method and system using assertion-based verification, which tracks the priority of requests through a counter and mask, verifying the operation of an arbiter by establishing a relationship between the counter and the clock cycle of request output, allowing for exhaustive verification of starvation, deadlock, race-freedom, and fairness with less verification code and greater diversity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dynamic simulation-based verification is used to verify arbitration schemes, then verification coverage can be achieved, but verification time and complexity become intractable as the number of requestors grows
Solution Approach 1:
The patent extracts the essential verification objective (checking arbitration correctness) from the complex simulation process and implements it through a formal property checker that directly verifies arbitration properties without requiring exhaustive simulation of all possible request sequences
Solution Approach 2:
The patent replaces the mechanical simulation-based verification approach with a formal logical verification system using property checkers and assertions that can mathematically prove arbitration correctness without time-consuming simulation
2Reliability
If dynamic simulation-based verification is used to verify arbitration schemes, then verification coverage can be achieved, but verification code complexity increases significantly
Solution Approach 1:
The patent extracts the core verification logic into formal property specifications that are separate from the arbitration implementation, allowing independent verification without complex simulation code
Solution Approach 2:
The patent uses formal property checkers that can be applied to multiple arbitration schemes without requiring custom verification code for each case, reducing overall verification complexity
3Reliability
If exhaustive testing is performed to verify arbitration correctness with respect to both priority selection and first-come-first-served selection, then verification completeness can be achieved, but the verification task becomes intractable
Solution Approach 1:
The patent segments the verification task into distinct formal properties: one for priority-based arbitration correctness and another for first-come-first-served arbitration correctness, allowing each to be verified independently through targeted assertions
Solution Approach 2:
The patent replaces exhaustive mechanical testing with formal logical verification that can prove correctness of both priority selection and first-come-first-served selection through mathematical assertions rather than brute-force simulation
Data Source
AI summary
Operation of an arbiter in a hardware design is verified. The arbiter receives a plurality of requests over a plurality of clock cycles, including a monitored request and outputs the requests in priority order. The requests received by and output from the arbiter in each clock cycle are identified. The priority of the watched request relative to other pending requests in the arbiter is then tracked using a counter that is updated based on the requests input to and output from the arbiter in each clock cycle and a mask identifying the relative priority of requests received by the arbiter in the same clock cycle. The operation of the arbiter is verified using an assertion which establishes a relationship between the counter and the clock cycle in which the watched request is output from the arbiter.