Arbiter for Embedded Processor Block Core in FPGA
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Solution Overview
Problem
Integrated circuit devices, specifically FPGAs, face performance limitations due to disparities between embedded processor parameters and programmable logic parameters, leading to bottlenecks and reduced flexibility when using ASIC cores for memory controllers or peripherals, which compromises overall performance and design flexibility.
Innovation Solution
The implementation of a processor block ASIC core with a crossbar switch and bridge architecture, incorporating an arbiter for arbitration protocols, allows for efficient access management between master devices and core logic, enabling improved performance without sacrificing design flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If embedded processors are designed apart from PLDs with higher operating frequencies, then processor performance is improved, but compatibility and synchronization with programmable logic deteriorates
Solution Approach 1:
The patent introduces an arbitration mechanism as an intermediary between the high-speed embedded processor and the slower programmable logic. The arbiter manages access to shared resources, coordinating transactions between the processor and PLD components, enabling the processor to operate at higher frequencies while maintaining reliable synchronization with the programmable logic through controlled access protocols
2Productivity
If ASIC cores are used for memory controllers or peripherals, then performance is improved, but design flexibility deteriorates
Solution Approach 1:
The patent implements a dynamic arbitration system that can adapt to different design requirements. The arbiter supports configurable arbitration policies and can dynamically adjust access management based on the specific application needs, allowing the same ASIC core architecture to maintain both high performance and design flexibility through programmable control parameters
3Device complexity
If direct interfaces are used between embedded processor and FPGA fabric, then connectivity is simplified, but performance bottleneck increases
Solution Approach 1:
The arbitration mechanism serves as an intermediary layer between the embedded processor and FPGA fabric interfaces. It manages access to shared resources, prioritizes critical transactions, and coordinates data flow, thereby eliminating performance bottlenecks while maintaining relatively simple interface architecture through intelligent control rather than complex hardware
Data Source
AI summary
Arbitration for a processor block core is described. Master devices are associated with a processor block core embedded in a host integrated circuit (“IC”). The master devices are coupled to core logic of the host IC via a crossbar switch and a bridge, which are part of the processor block core. The crossbar switch includes an arbiter. An arbitration protocol is selected from among a plurality of arbitration protocols for use by the arbiter. Pending transactions having are polled for access to the bridge for arbitration using the arbitration protocol selected.