Arbiter Circuit for Memory Sub-system Command Arbitration
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Solution Overview
Problem
Conventional memory sub-systems do not effectively manage multiple physical functions over a PCIe interface, leading to inefficiencies in command arbitration and bandwidth utilization, resulting in suboptimal performance and latency.
Innovation Solution
A memory sub-system utilizing an arbiter circuit that arbitrates commands from multiple physical functions, allowing runtime workload adjustments based on statistics, ensuring fair distribution of commands across physical functions and optimizing bandwidth usage by scattering commands into timing windows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional memory sub-systems manage multiple physical functions without effective arbitration, then device complexity is reduced, but bandwidth utilization and performance deteriorate
Solution Approach 1:
The arbiter circuit is segmented into multiple independent arbitration units, each handling specific physical functions. This segmentation allows parallel arbitration operations for different PFs, improving bandwidth utilization while keeping each arbitration unit relatively simple in structure.
Solution Approach 2:
The arbiter circuit implements dynamic arbitration by adjusting arbitration parameters and command scheduling based on real-time workload statistics. This dynamic adaptation optimizes bandwidth utilization for varying workload patterns without requiring a fundamentally complex static structure.
2Loss of time
If commands are arbitrated without scattering into timing windows, then device complexity is reduced, but latency increases
Solution Approach 1:
The arbiter circuit implements periodic timing windows for command arbitration, where commands from different physical functions are scattered into specific time slots. This periodic scattering reduces command latency by ensuring fair and predictable service times while maintaining manageable circuit complexity through regular scheduling patterns.
3Reliability
If fair distribution of commands is implemented across physical functions, then quality of service improves, but arbitration complexity increases
Solution Approach 1:
The arbiter circuit uses feedback mechanisms that monitor command queues and workload statistics from multiple physical functions. Based on this feedback, the arbiter dynamically adjusts command distribution to ensure fair quality of service while avoiding unnecessary complexity through intelligent, data-driven arbitration decisions.
Solution Approach 2:
The arbiter circuit changes arbitration parameters such as command selection weights and timing window allocations based on observed workload characteristics. This parameter adaptation ensures fair quality of service across different physical functions while maintaining relatively simple arbitration logic that responds to changing conditions.
Data Source
AI summary
A system controller of a memory system can present multiple physical functions (PFs) to a host computing system. The system controller can store commands from the host in separate queues and uses an arbiter circuit to issue commands. The arbiter can determine a difference value between a quota of commands and a count of commands issued from a respective queue. The quota is derived from a share specified by the host for the respective PF. The arbiter circuit determines a subset of queues by excluding queues that are empty and queues having a negative difference value. The arbiter circuit can randomly choose a selected queue from the subset and issue a command from the selected queue.