Arbiter-Based Processor Architecture for Dynamic Pipeline Stage Reduction
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Solution Overview
Problem
Conventional network processors experience low data processing efficiency due to their fixed pipeline architecture, leading to increased time delays and reduced performance.
Innovation Solution
A data processing method and processor architecture that utilizes an arbiter to send data to multiple processing circuits, allowing each circuit to process and forward data to the next stage, thereby reducing the number of pipeline stages required for data processing from (m+1) to m, and enabling efficient data processing by skipping unnecessary processing stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is processed through a fixed pipeline architecture with multiple sequential stages, then each processing circuit can perform its specific function, but the number of pipeline stages increases time delays and reduces processing efficiency
Solution Approach 1:
The patent transforms the fixed sequential pipeline architecture into a dynamic architecture where the processing path is determined by data characteristics. The arbiter dynamically selects which processing circuits to activate based on the input data type, allowing the system to adapt its structure rather than following a rigid predetermined path. This resolves the contradiction by maintaining reliability through selective processing while reducing time delays by eliminating unnecessary processing stages.
Solution Approach 2:
The patent extracts and removes unnecessary processing stages from the data path based on the specific data being processed. Instead of forcing all data through all pipeline stages, the system identifies and eliminates redundant processing circuits that are not needed for particular data types. This extraction principle directly reduces the number of pipeline stages and time delays while preserving the necessary processing functions for reliability.
2Adaptability or versatility
If all processing circuits are connected in a fixed pipeline sequence, then comprehensive processing functions are available, but the complexity of the pipeline architecture increases and efficiency decreases
Solution Approach 1:
The patent implements a universal arbiter component that can direct data to multiple different processing circuits based on data characteristics. This single arbiter provides multi-functional control, replacing the need for dedicated control logic in each pipeline stage. The processing circuits themselves are designed to handle multiple data types, reducing the overall complexity while maintaining comprehensive processing capabilities across the system.
Solution Approach 2:
The patent segments the processing functions into independent, modular processing circuits that can be selectively activated. Rather than a monolithic pipeline where all stages must be present, the system divides processing into discrete functional blocks that can be independently configured and activated based on data needs. This segmentation reduces architectural complexity by allowing selective instantiation of processing stages while maintaining versatility through the ability to combine different segments.
3Reliability
If data must pass through all (m+1) processing stages, then complete processing is ensured, but the processing speed and efficiency are reduced
Solution Approach 1:
The patent enables the data processing path to skip unnecessary processing stages by using the arbiter to directly route data to the appropriate processing circuits. When certain processing functions are not needed for a particular data type, the system skips those stages entirely rather than forcing data through all (m+1) stages. This skipping mechanism maintains complete processing for necessary functions while dramatically improving processing efficiency by eliminating redundant stages.
Data Source
AI summary
Disclosed are a data processing method, a processor, and a data processing device. The method comprises: an arbiter sends data D(a,1) to a first processing circuit; the first processing circuit processes the data D(a,1) to obtain data D(1,2), the first processing circuit being a processing circuit among m processing circuits; the first processing circuit sends the data D(1,2) to a second processing circuit; the second processing circuit to an mth processing circuit separately process the received data; and the arbiter receives data D(m,a) sent by the mth processing circuit. The processor comprises an arbiter and a first processing circuit to an (m+1)th processing circuit. Each processing circuit in the first processing circuit to the (m+1)th processing circuit can receive first data to be processed sent by the arbiter, and process the first data to be processed. The scheme is helpful to improve efficiency of data processing.