Arbiter-Based Progress Level Arbitration for Parallel Computing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In parallel computing systems, processors that complete their tasks earlier than others wait unnecessarily, leading to reduced overall processing performance due to delays and conflicts in external accessing and communication between processors.
Innovation Solution
An apparatus comprising an arbiter and multiple arithmetic processors, where each processor includes a measuring circuit to track progress levels, allowing the arbiter to arbitrate access requests based on these levels to prioritize and balance the processing workload, ensuring that processors with lower progress levels are given access rights first.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If processors execute external accesses and communicate in parallel without arbitration based on progress levels, then processing speed is improved, but processing performance deteriorates due to delays and conflicts
Solution Approach 1:
An arbiter is introduced as an intermediary component to manage access requests from multiple arithmetic processors to external devices. The arbiter receives progress level information from each processor and arbitrates access requests based on comparing these progress levels, thereby mediating between the processors' need for parallel access and the external device's limited capacity, resolving conflicts without sacrificing overall processing performance
Solution Approach 2:
The system changes the arbitration parameter from traditional methods (such as round-robin or priority-based) to progress level-based arbitration. Each processor's progress level is dynamically measured and used as the basis for arbitration decisions, allowing the system to adapt access rights to the actual execution state of each processor, thereby balancing parallel access needs with overall performance
2Device complexity
If processors wait for all processors to complete before allocating new tasks, then task allocation simplicity is maintained, but productivity is reduced due to unnecessary waiting
Solution Approach 1:
The arbiter performs preliminary arbitration of access requests based on current progress levels before processors complete their current tasks. By proactively managing access rights and balancing progress levels during execution, the system prepares for efficient next task allocation without requiring all processors to wait, thus improving throughput while maintaining manageable complexity
Solution Approach 2:
The system implements feedback through measuring circuits that continuously monitor and report progress levels of each processor to the arbiter. This feedback mechanism enables dynamic task allocation decisions based on real-time processor states, allowing the system to allocate new tasks more efficiently without excessive complexity by responding to actual progress information
3Productivity
If processors are allocated tasks in parallel, then processing efficiency is improved, but time difference between completion of different processors increases
Solution Approach 1:
The arbitration system dynamically adjusts access rights based on real-time progress level measurements from each processor. Instead of static task allocation, the arbiter continuously adapts which processor receives external access rights based on their current progress levels, creating a dynamic balancing effect that reduces completion time differences while maintaining parallel processing efficiency
Solution Approach 2:
The system works to maintain equipotentiality in progress levels across processors by using the arbiter to balance access to external devices. By giving external access rights to processors with lower progress levels, the system equalizes the workload and progress states of different processors, reducing the time difference between their completions while preserving parallel efficiency
Data Source
AI summary
An apparatus includes an arbiter and a plurality of arithmetic processors, each including an arithmetic circuit and a measuring circuit. The arithmetic circuit executes an arithmetic process, and the measuring circuit measures a progress level indicating a progress of the arithmetic process executed by the arithmetic circuit. Upon receiving access requests to an external device from first arithmetic processors included in the plurality of arithmetic processors, the arbiter arbitrates the access requests, based on a result of comparing the progress levels measured by the measuring circuits of the first arithmetic processors.