Arbiter Pseudo-Grant Signal Reduces Bus Waiting Time
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Solution Overview
Problem
Conventional arbitration mechanisms in bus bandwidth management result in wasted grants and degraded bandwidth due to waiting times caused by the inability to prepare target slaves for data access prior to bus ownership, limiting the effectiveness of techniques like bank interleaving and requiring additional pins for cycle type signals.
Innovation Solution
The introduction of a pseudo-grant signal system where the arbiter generates a pseudo-grant signal to all requesting master units, allowing them to supply target information before actual arbitration, enabling the target slave to prepare for data transfer and reducing waiting times by modifying the order of arbitration signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional arbitration mechanisms are used where the arbiter grants bus ownership to a master after arbitration, then the arbitration process is simple and straightforward, but the target slave cannot prepare for data transfer in advance, resulting in waiting time delays and degraded bus bandwidth
Solution Approach 1:
The patent applies preliminary action by allowing the master to drive address and control information to the arbiter before the actual arbitration is complete. The arbiter receives this information in advance and uses it to determine arbitration priority, enabling the target slave to prepare for data transfer beforehand. This eliminates the waiting time between arbitration completion and data transfer initiation, thereby improving bus bandwidth without adding complexity to the arbitration process
2Productivity
If bank interleaving is used to divide memory into several banks for overlapping operations, then bus bandwidth is improved through simultaneous access to multiple banks, but the waiting time delay still exists because the request to the target slave cannot be sent in advance
Solution Approach 1:
The patent eliminates the waiting time in bank interleaving operations by enabling preliminary action. The master can drive address and control information to the arbiter before arbitration is complete, allowing the arbiter to forward this information to the appropriate memory bank in advance. This enables the memory bank to prepare for data transfer before the arbitration is finalized, removing the waiting time delay that limits bank interleaving effectiveness
3Reliability
If a master generates a cycle type signal at the same time as a request to indicate the specific target resource and access type, then the arbiter can determine priority more accurately and avoid target slave retry cycles, but additional pins are required and the waiting time delay still exists
Solution Approach 1:
The patent applies universality by making the existing HADDRN signal serve multiple functions. Instead of requiring separate cycle type signals and additional pins, the arbiter interprets the address information already present on HADDRN to determine both the target slave identity and the access type (read/write, burst/non-burst). This multi-functional use of the address signal achieves accurate arbitration without adding any physical pins or increasing device complexity
Data Source
AI summary
An arbiter, a system, and a method for generating a pseudo-grant signal in response to a request and receiving target information in response to the pseudo-grant signal. The pseudo-grant signal reduces or eliminates waiting time.